The RISC-V Workshop held in Zurich, Switzerland, from June 11th to 13th brought several announcements related to the popular open-source ISA; more news concern partnerships in the DMS and autonomous vehicle area. This week and the next, events are making Long Beach the capital of artificial intelligence; meanwhile, research institutes and universities keep studying semiconductor technology and new materials.

RISC-V ecosystem expanding

Right after crossing the 100-design win threshold, SiFive has announced it raised $65.4 million in a Series D round from a group of investors that now includes Qualcomm Ventures. Another aspect of RISC-V growing traction is the expansion of its ecosystem. Andes Technology has just introduced its RISC-V FreeStart program, promising “an easy and fast way” to build a SoC based on the commercial-grade RISC-V CPU core N22, available for free download. According to Andes, SoC designers using the N22 can skip the verification tasks required by open source RISC-V CPUs, which offer limited features and lack documentation. Supporting designers who plan to use RISC-V is also the goal of the newly formed OpenHW Group, a not-for-profit global organization aiming to boost the adoption of open-source processors. OpenHW Group will pursue this missione by providing a platform for collaboration, creating a focal point for ecosystem development, and offering open-source IP for processor cores. As an example, for RISC-V-based processors, the organization is introducing the CORE-V family of cores, which offers a manufacturability assurance. Inaugural OpenHW sponsors include Alibaba, Bluespec, CMC Microsystems, Embecosm, ETH Zurich (university), GreenWaves, Imperas, Metrics, Mythic AI, NXP, Onespin, Silicon Labs and Thales.

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