Major stories this week: new CPUs and MCUs; yield analysis; large chip prototyping; autonomous driving

The Computex show in Taipei has brought announcements from Intel, AMD and Arm, while MCU suppliers are also introducing significant innovations. EDA vendors are making news too, preannouncing some of the highlights of the upcoming DAC. And research efforts make autonomous driving a bit closer.

10th Gen Intel Core processors

Many of the innovations announced by Intel at Computex are targeted at laptops, with main course being the first 10th Gen Intel Core processors featuring Intel Deep Learning Boost. Built on the company’s 10nm process technology, new Sunny Cove core architecture and new Gen11 graphics engine, the 10th Gen Intel Core range will span from i3 to i7, with up to 4 cores and 8 threads, up to 4.1 max turbo frequency and up to 1.1 GHz graphics frequency. The new family targets thin-and-light laptops and ‘2 in 1s’, claiming a sharp performance increase over previous generation on every front: AI workloads, graphics (including 4K HDR), wireless connectivity (more than 1 Gbps with Wi-Fi 6). These SoCs integrate many on-chip functions, including a Gaussian Network Accelerator, Thunderbolt 3 and Wi-Fi 6. Intel also unveiled the 1.0 target specification of its Project Athena, aimed at improving the experience of laptop users. Requirements (called ‘key experience indicators’) include 16 or more hours of battery life in local video playback mode, 9 or more hours of battery life under real-world performance conditions, system wake from sleep in less than 1 second. Announcements include the new Intel Performance Maximizer, an automated overclocking tool for unlocked 9th Gen Intel Core desktop processors “that brings overclocking to the masses”, as stated in a press release.

10th Gen Intel Core processor. Image credit: Intel Corporation

AMD’s new core architecture and desktop processor

At Computex, rival processor supplier AMD mainly focused on processors for desktop PCs, stressing the use of a 7nm process and a chiplet design approach. Among AMD’s major announcements, a new core architecture called ‘Zen 2’ offering up to a 15% increase in instructions per clock over the predecessor Zen architecture. Powering next-generation Ryzen and EPYC processors, the new core features other design improvements including larger cache sizes and a redesigned floating-point engine. AMD has also unveiled the 3rd Gen Ryzen desktop processor, that the company describes as “the most advanced desktop processor in the world”. It offers a large amount of performance-critical on-die cache and support for PCIe 4.0. Flagship product of the new generation is Ryzen 93900X, a 12 core/24 thread processor. News from AMD include a novel gaming architecture called RDNA, which will power the upcoming 7nm Radeon RX 5700-series graphics cards featuring GDDR6 memory and support for the PCIe 4.0 interface.

Also at Computex, Arm discussed new mobile IP focusing on artificial intelligence: the Cortex-A77 CPU, the Mali-G77 GPU, and enhancements to the Arm ML processor. Support to early adopters of the Arm Cortex-A77 CPU has already been announced by both Cadence and Synopsys.

MCUs integrating high precision AFE, math accelerators

Though not as glamourous as gaming chips, blue-collar microcontrollers are also evolving, reaching a higher integration level to simplify today’s demanding applications. A new family of 32-bit MCUs from Renesas, the RX23E-A Group 32, features an on-chip high precision analog frontend enabling measurements of temperature, pressure, weight and flow with better than 0.1% precision without calibration. These chips are mainly targeted at manufacturing (e.g. robotics) and T&M applications.

Renesas RX23E-A Group 32 MCUs. Image credit: Renesas

STMicroelectronics’ new STM32G4 microcontrollers family – built on a 170MHz implementation of the Arm Cortex-M4 core – introduces two new hardware mathematical accelerators to boost processing of applications that use Cordic1 and filtering functions. Accelerators speed up calculations such as trigonometry for energy-saving motor controls in appliances or air conditioners and filtering for signal conditioning or digital power control.

STMicroelectronics STM32G4 MCUs. Image credit: STMicroelectronics

Pre-silicon design yield analysis and other news from Synopsys

Moving from PPA to PPAY, or, in other words, adding yield as a fourth design quality metric besides power, performance and area: this is the concept behind PrimeYield, the new Synopsys solution for pre-silicon design yield analysis. Claiming a 100X-1000X speed boost compared to traditional Monte Carlo simulation, it is based on statistical methods and machine learning technology, and can scale to SoCs with billions of transistors. Also from Synopsys, a Datapath Validation app that leverages HECTOR technology to deliver exhaustive formal verification closure on datapath-intensive designs. According to the company, the app reaches a 100X speed-up over conventional techniques in formal verification between a reference C/C++ algorithm and RTL design implementation, and enables exhaustive functional verification in situations previously deemed impractical. Synopsys has also announced an addition to its ZeBu Server 4 emulation platform: the new ZeBu Power Analyzer solution for software-driven SoC power analysis, that allows to systematically analyze power usage of designs when executing billion-cycle, complex software applications. The company claims results 1,000 times faster than traditional simulation-based methods.

Prototyping billion-gate designs at 5MHz

Cadence has announced the Protium X1 Enterprise Prototyping Platform, described as the first data center-optimized FPGA-based prototyping system providing multi-MHz speed for early software development, hardware/software regressions and full system validation. The Protium X1 architecture is applicable to a wide range of design sizes and applications, from multi-billion-gate AI and 5G chips to single-FPGA IoT chips and IP blocks. “For the first time, billion-gate designs can be executed at up to 5MHz”, stated a Cadence officer in a press release.

Towards autonomous driving

Confirming the growing involvement of car makers in the semiconductor value chain, Audi has recently joined SEMI. Meanwhile, researchers are developing solutions based on neural networks that will help unmanned vehicles in unexpected situations, a key requirement for future autonomous driving cars. MIT is studying an autonomous control system that learns the steering patterns of human drivers, thus gaining the capability of driving a car in a brand-new area. The system uses camera images to predict road structures: for instance, it identifies a distant stop sign as an upcoming intersection. Researchers from Daimler and the University of Kassel have developed a system to improve radar-based classification of road users, including previously unseen classes. As the scientists note, discriminating between a bus and a truck is not very important for path planning, but distinguishing those vehicles from a train – or a skateboarder from a regular pedestrian – is essential, although they look similar when observed by a radar sensor.

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