Major stories this week: Interconnect fabric, RISC-V ecosystem, ARM Neoverse, USB4

Three recent and unrelated events confirm the ever-growing importance of the technologies and architectures used to connect processing elements at all levels – within a chip, among chips, within a datacenter. Other significant announcements made over the past few days concern the growing RISC-V ecosystem; the first Arm Neoverse system development platform on TSMC 7nm process technology; and EDA/T&M vendors getting ready for USB4.

Bit Traffic

On March 11, the GPU vendor Nvidia announced the acquisition of Mellanox, a key player in high-performance interconnect technologies. With this acquisition, Nvidia aims at optimizing datacenter-scale workloads across the entire computing, networking and storage stack to achieve higher performance, greater utilization and lower operating cost. According to Nvidia, datacenters in the future will be architected as giant compute engines with tens of thousands of compute nodes, designed holistically with their interconnects for optimal performance. Hence the strategic importance of joining forces with Mellanox.

Two days later, on March 13, the Open Compute Project announced a sub-project aimed to creating an open multi-chiplet architecture targeted for SoC designs and domain-specific accelerators (such as co-processors for networking, security, storage, machine learning and inferencing). The Open Domain-Specific Architecture (ODSA) sub-project will define an open interface and architecture that enables the mixing and matching of available silicon die from different suppliers onto a single SoC for datacenter applications. The major driver towards using chiplets to build an SoC is cost reduction; the fabric connecting chiplets will clearly become an enabling factor to this goal. Companies participating in the workshop that proposed the ODSA sub-project included Netronome, Achronix, AveraSemi, Facebook, Kandou, NXP, TitanIC and zGlue.

Also on March 13, according to an authoritative publication, Facebook reportedly bought Sonics, a network-on-chip IP vendor. As we write, Facebook has not issued any official press release about this yet; however, the Sonics website currently displays a message citing a “next chapter” in the company’s history. If confirmed, the acquisition of Sonics by Facebook would indicate that the social media giant attaches special importance to the network-on-chip intellectual property, a key technology for SoCs. It would also be another example of how the Internet heavyweights – including Google and Amazon – are becoming increasingly interested in silicon.

A Growing RISC-V Ecosystem

Artificial intelligence applications are among the targets of some recent developments in the open source arena. On March 12 at the RISC-V Workshop Taiwan, Andes Technology described its new 32-bit A25MP and 64-bit AX25MP RISC-V multicore, cache-coherent processors – the first commercial RISC-V cores with comprehensive DSP instruction extension. Andes points out that multiple processor cores working in parallel empower applications such as artificial intelligence and Advanced Driver-Assistance Systems (ADAS) to boost performance of their computation intensive tasks significantly, while hardware managed cache coherence simplifies software design. Supporting up to four CPU cores, the A25MP and AX25MP operate at over 1GHz in 28nm process with Linux symmetric multiprocessing (SMP) support.

A day earlier, on March 11, The Linux Foundation announced its intent to form the CHIPS Alliance project (where CHIPS stands for Common Hardware for Interfaces, Processors and Systems) to promote the development of open source code for the design of RISC-V-based chips. Early CHIPS Alliance backers include Esperanto Technologies, Google, SiFive and Western Digital. Founding members explain the need for this new organization by pointing out that the RISC-V Foundation only focuses on the instruction set architectures and does not specify actual implementations, while the CHIPS Alliance focuses exactly on microarchitecture implementations. Participants of the CHIPS Alliance will therefore be able to download source code and compile binaries to get Linux running and offer a fully functional CPU or SoC design with RISC-V. Alliance backers have already announced their planned contributions: Google is planning to contribute a Universal Verification Methodology (UVM)-based instruction stream generator environment for RISC-V cores; Western Digital will provide their 32-bit SweRV Core, together with a test bench, SweRV Instruction set simulator, and specification of the OmniXtend cache coherence protocol; SiFive will contribute and maintain Diplomacy, the SoC parameter negotiation framework.

Arm Neoverse on TSMC 7nm Process Technology

The Arm ecosystems is also making news. On March 12, Arm, Cadence Design Systems and Xilinx announced the delivery of a new development platform based on Arm Neoverse N1, silicon-proven on TSMC’s 7nm FinFET process technology. The Neoverse N1 System Development Platform (SDP) is also the industry’s first 7nm infrastructure development platform enabling asymmetrical compute acceleration via the CCIX interconnect architecture. It includes a Neoverse N1-based SoC with an operating frequency of up to 3GHz, full-sized caches and optimized system IP. Aimed for cloud-to-edge infrastructure, the platform targets applications such as machine learning, artificial intelligence and data analytics. The development platform was implemented and verified using a full Cadence tool flow in TSMC’s 7nm FinFET process technology and provides connectivity to Xilinx VirtexUltraScale+ FPGAs over the CCIX chip-to-chip coherent interconnect protocol via the Xilinx Alveo U280 CCIX accelerator card.

Getting ready for USB4

Just ten days after the announcement of the USB4 specifications, major EDA vendors are ready to offer the necessary verification IP. On March 14, both Cadence Design Systems and Synopsys announced the availability of their respective VIPs in support of the new standard. Synopsys is also offering a Subsystem Verification Solution and a UVM source code test suite. Also getting ready for the latest version of the bus is Teledyne LeCroy, that has recently announced and demonstrated the first protocol analyzer platform for testing USB4 and Thunderbolt 3 systems. The USB4 architecture is based on the Thunderbolt protocol specification contributed by Intel. It doubles the bandwidth of USB and enables multiple simultaneous data and display protocols.

Category: EDACafe Editorial

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