Bob Smith, Executive DirectorBob Smith is Executive Director of the ESD Alliance responsible for its management and operations. Previously, Bob was senior vice president of Marketing and Business Development at Uniquify, responsible for brand development, positioning, strategy and business development activities. Bob began his career in high tech as an analog design engineer working at Hewlett Packard. Since then, he has spent more than 30 years in various roles in marketing, business development and executive management primarily working with startup and early stage companies. These companies include IKOS Systems, Synopsys, LogicVision, and Magma Design Automation. He was a member of the IPO teams that took Synopsys public in 1992 and Magma public in 2001. Bob received his BSEE from U.C. Davis and his MSEE from Stanford University. « Less
Bob Smith, Executive DirectorBob Smith is Executive Director of the ESD Alliance responsible for its management and operations. Previously, Bob was senior vice president of Marketing and Business Development at Uniquify, responsible for brand development, positioning, strategy and business development activities. Bob began his … More »
June 7th, 2023 by Bob Smith, Executive Director
 A reminder that nominations for the Phil Kaufman Award and the Phil Kaufman Hall of Fame close Friday, June 30.
 The annual Phil Kaufman Award for Distinguished Contributions to Electronic System Design, sponsored by the Electronic System Design Alliance (ESD Alliance) and the IEEE Council on Electronic Design Automation (CEDA), honor individuals who have made a visible and lasting impact on electronic design. Their influence could be as a technologist or engineering leader, a professional in education and mentorship or a C-level executive or someone promoting the industry or setting industry direction.
The Phil Kaufman Hall of Fame, introduced in 2021 by the ESD Alliance and the IEEE CEDA, pays tribute to deceased individuals who made significant and noteworthy creative, entrepreneurial and innovative contributions and helped our community’s growth. The designation was established due to an IEEE policy set where only living contributors are eligible to receive awards. Our first three recipients were Jim Hogan (1951–2021) and Ed McCluskey (1929-2016) in 2021 and Mark Templeton (1958-2016) in 2022. Jim Hogan was managing partner of Vista Ventures, LLC., and an experienced senior executive who worked in the semiconductor design and manufacturing industry for more than 40 years. Ed McCluskey, a professor at Stanford University, sustained a relentless pace of fundamental contributions for efficient and robust design, high-quality testing and reliable operation of digital systems. Mark Templeton (1958-2016), CEO of Artisan Components (now Arm), helped develop a fledgling IP industry into a multi-billion dollar business.
Read the rest of Looming Deadline for Phil Kaufman Award, Phil Kaufman Hall of Fame Nominations
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May 18th, 2023 by Bob Smith, Executive Director
Note: Accellera’s Lu Dai is chair of its Board of Directors as well as Senior Director of Technical Standards at Qualcomm. Lu has quite a lot to say about the importance and efficacy of semiconductor industry standards. Below is the Q&A blog post from a recent discussion we had that appeared on the SEMI website earlier this month.
Accellera Systems Initiative – or Accellera – is a standards organization well-regarded by the electronic design automation (EDA) ecosystem that’s also served by the ESD Alliance, a SEMI Technology Community. Lu Dai, Senior Director of Technical Standards at Qualcomm, has chaired the Accellera Board of Directors since 2017. I recently spoke with Dai about the importance and efficacy of semiconductor industry standards.
Smith: Standards are a way of life in EDA and across the semiconductor industry. Why are they so important?
Dai: Accellera Standards represent a collaboration of the best ideas in the industry to support product development. They help build an ecosystem and foster innovation through sharing of ideas and practices instead of re-invention.
Smith: Accellera was formed when Open Verilog International and VHDL International, two important verification organizations, merged in 2000. What is Accellera’s greatest standards success to date?
Dai: Our SystemVerilog is our biggest success because it united Verilog and VHDL, the standards that started Accellera, though we’ve produced a number of compelling standards including Verilog, VHDL, System Verilog, SystemC, UPF and UVM, our most downloaded standard. It can be downloaded for free as part of our IEEE GET Program. Additionally, a video on UPF is the most watched of our videos worldwide. Among our forum discussions, SystemC is the most active of our standards.
Read the rest of Accellera Speeds the Path to Industry Standardization
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May 10th, 2023 by Bob Smith, Executive Director
The election results are in and it’s a pleasure to announce the ESD Alliance’s incoming Governing Council for the 2023-2025 term, a mix of returning council members and two new members.
We’re adding Niels Faché, vice president and general manager of Keysight, and John Lee, general manager and vice president of Ansys, as our two new members. Outgoing members are Dean Drako of IC Manage and Simon Segars. I would like to personally thank Dean and Simon for their many years of service to the ESD Alliance and their commitment to the industry.
Read the rest of ESD Alliance Elects 10-Member Governing Council, Including Executives from Ansys, Keysight
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May 3rd, 2023 by Bob Smith, Executive Director
Electronic System Design (ESD) industry revenue grew yet again, according to the latest Electronic Design Market Data (EDMD) report from the ESD Alliance, a SEMI Technology Community. ESD revenue increased 11.3% to $3,858.7 million in the fourth quarter of 2022, up from $3,468.2 million in the fourth quarter of 2021. The four-quarter moving average was 12.6%, a percentage based on comparisons for the most recent four quarters to the prior four.
The good news continues as all geographic regions recorded growth in the quarter with Asia Pacific (APAC)reporting a double-digit increase. APAC secured $1,397.5 million of ESD products and services in Q4 2022, a 17.9% increase growing the four-quarter moving average to 17.1%.
Read the rest of Electronic System Design Industry Logs $3.8 Billion in Revenue in Q4 2022, CEO Outlook May 18
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April 19th, 2023 by Bob Smith, Executive Director
You won’t want to miss this year’s CEO Outlook hosted by the ESD Alliance and sponsored by Keysight! It will take place Thursday, May 18, in Santa Clara, Calif. We have a notable list of panelists and Ed Sperling, editor in chief of Semiconductor Engineering, will moderate and lead the discussion about the current state and future of the chip design and semiconductor industries.
Our panelists are:
- Dean Drako, President and CEO of IC Manage
- Niels Faché, VP and GM at Keysight EDA
- John Kibarian, President and CEO of PDF Solutions
- John Lee, GM and VP at Ansys
- Prakash Narain, President and CEO of Real Intent
- Joe Sawicki, Executive Vice President of Siemens EDA
- Simon Segars, Chair, ESD Alliance Governing Council
As always, we encourage audience participation and feedback, so join us and bring your questions and observations.
Read the rest of A Notable Lineup for 2023 CEO Outlook May 18
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April 6th, 2023 by Bob Smith, Executive Director
Our yearly CEO Outlook will be held Thursday, May 18, in Santa Clara, Calif., with Ed Sperling, editor in chief of Semiconductor Engineering, serving as moderator. Ed will lead a panel discussion about the current state and future of the chip design and semiconductor industries. We’ll announce the panelist lineup soon.
The in-person event, co-sponsored by Keysight, will be held at Agilent’s Building 5 at 5301 Stevens Creek Blvd. in Santa Clara beginning at 5:30 p.m. with networking, food and beverages. The hour-long panel starts at 6:30 p.m. and is open to ESD Alliance and SEMI members at no cost. Pricing for non-members is $50 per person. Details and registration can be found at: https://bit.ly/3UbF1Lf
The ESD Alliance Annual Membership meeting for members will be held prior to the start of the CEO Outlook beginning at 5 p.m. Non-members with tickets to the CEO Outlook are welcome to sit in on the membership meeting.
Read the rest of Mark the Calendar: 2023 CEO Outlook May 18
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March 29th, 2023 by Bob Smith, Executive Director
Originally scheduled to be held in March, “The Impact of New Regulations on the Semiconductor Design Ecosystem,” was postponed due to scheduling conflicts to Wednesday, April 26, from 8:30-11am at Cadence’s corporate headquarters in San Jose, Calif.
The seminar, presented by SEMI’s ESD Alliance Export Committee, will be hosted by Ada Loo, chair of the ESD Export Committee and Cadence’s Group Director and Associate General Counsel. Attendees will learn why and how governments implement trade controls and what “exports” are and how they take place in different business contexts. Explanations will help clarify common due diligence methods, such as customer screening, that U.S. companies use to incorporate regulatory compliance into their business processes. The seminar also will focus on recent regulatory updates that address current issues including U.S.-China trade relations and the anticipated effects of those regulations on the US semiconductor design ecosystem.
Read the rest of Rescheduled! Export Seminar on Impact of New Regulations on the Semiconductor Design Ecosystem
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March 21st, 2023 by Paul Cohen
The design and manufacture of today’s semiconductor chips is a complex process, requiring advanced software tools throughout the design to manufacturing flow. These tools require a team of talented engineers to develop and maintain. As the industry advances to smaller geometries and heterogeneous integration, new challenges arise requiring more research and development of the software used throughout the design ecosystem. These efforts are funded through the sale and licensing of the software.
One of the ongoing efforts of the Electronic System Design Alliance (ESD Alliance), a SEMI Technology Community, is the License Management and Anti-Piracy Committee (LMA). Part of the committee’s purpose is to help reduce the incidence of unauthorized use (piracy) of this complex software. Unauthorized use negatively impacts both the tool vendors and customers. It deprives the software developers of revenue for their continuing efforts to develop new products that address the increasingly complex design ecosystem. Software piracy impacts the legitimate users of the software in two ways. First, the vendors may need to increase prices to be able to continue their R&D of new products and functionality. Second, it provides an unfair competitive advantage to those companies who are not paying for the software.
Read the rest of License Server Certification Task Force Formed
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March 13th, 2023 by Bob Smith, Executive Director
Note: I recently talked with Jean-Marie Brunet, Vice President and General Manager of the Siemens Hardware-Assisted Verification business unit, about the growing use of chiplets. He has a unique perspective that’s captured below in a blog post I wrote for 3D InCites.
 Jean-Marie Brunet, Vice President and General Manager of the Siemens Hardware-Assisted Verification business unit finds himself and his group in a unique situation when it comes to the topic of chiplets. The group designs a chiplet for their own products and sells those products to verification engineers who are verifying chiplet designs.
I recently had a conversation with Jean-Marie to get his perspective on chiplets and why he believes they are leading an epic chiplet evolution.
Smith: A significant challenge to chiplet adoption is scaling. Is that the biggest challenge or are there more pressing challenges?
Brunet: It’s a big topic. First, let me explain why. I manage an organization that develop hardware verification technology to the market –– emulators and FPGA prototyping hardware.
In the case of the emulator, we create all parts of the emulator. We build a very large device with a complex hardware architecture that must run a large amount of software. By developing our own hardware, we understand scaling challenges.
In terms of scaling, there is a lot of talk about how Moore’s Law is dead. No, Moore’s Law is doing just fine. Today semiconductor companies are designing for two or three nanometer process technology that uses a different type of transistor so it’s very expensive to go to an advanced node.
Read the rest of An Epic Chiplet Evolution
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February 28th, 2023 by Bob Smith, Executive Director
Please join us as Ada Loo, chair of our Export Committee and Group Director and Associate General Counsel at Cadence Design Systems, hosts an export seminar on the impact of new regulations on the electronic systems design ecosystem. The breakfast meeting will be held Tuesday, March 28, from 8:30am until 11:30am at Cadence’s corporate headquarters in San Jose.
The session will feature the Cadence Government and Trade Group addressing general trade compliance concepts, how export control and sanction regulations affect the industry and current trends and emerging issues. Audience questions will be encouraged.
Speakers are Ada Loo and William Duffy, Cadence’s Corporate Counsel.
Read the rest of Join Us for “The Impact of New Regulations on EDA and SIP” Export Seminar March 28
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