Note: I turn this week’s Bridging the Frontier blog over to Anirudh Devgan, President and CEO, Cadence Design Systems and ESD Alliance Governing Council Member, to give us his view of Computational Software. His viewpoint first appeared in the ESD Alliance newsletter distributed at SEMICON West/DAC. It’s now available on the ESD Alliance website.

I truly believe this is the golden era of semiconductors. Nearly everything in our lives is becoming digital and everything digital requires semiconductors. Today, the industry is about $500B and is on the path to $1T in the next few years. The overall semiconductor industry has always been cyclical, but I believe it is becoming less so, in fact, it is rapidly becoming a fundamental growth industry.

The generation and processing of data, especially unstructured data, is impacting everything from device compute, to the edge and to the cloud. It is transformational in many ways and has led to the emergence of data-driven algorithms and AI semiconductor compute. The motivation is to process the unstructured data and get intelligence out of it. Technology innovations are enabling waves of new products for many applications such as automotive, mobile, manufacturing, healthcare and even the rise of the metaverse. This fundamental trend will continue for decades, and it’s a thrill to be in the middle of it all.

Another growth driver is systems companies’ in-house semiconductor development to optimize the application architectures to maximize performance, address power efficiencies and improve the safety and security of their end products, plus the added benefit of increased control of their supply chain. Also emerging is a new era of system in a package (SiP) and the creation of chiplets. As Moore’s law matures, this will provide a massive improvement in system performance while focusing on the compute portion that benefits most from new process node technologies. EDA must provide an integrated platform to design and analyze all the aspects of SiP and chiplets, which is quite a challenge, with Die-to-Die IP playing a critical role. Overall these enable designers to combine the benefits of advanced semiconductor node innovation with other architectural changes to increase data processing throughput within power and form factor constraints. (more…)

Note: As SEMICON West and DAC wind down this week, let’s have a look at a Q&A blog post I did on Metis Microsystems, a member of the ESD Alliance, that appeared on the SEMI Website.

Any chip design group with a project specification that prioritizes improved energy efficiency and performance may want to learn more about Metis Microsystems, a member of the ESD Alliance, a SEMI Technology Community.

This East Coast startup founded in 2017 develops advanced CMOS Memory and Arithmetic component intellectual property (IP) to improve energy efficiency and performance of processors. Metis’ circuit IP harvests a device’s transient data to alleviate circuit limits on CMOS scaling. Applications for the technology are relevant to semiconductor markets limited by compute performance and energy efficiency.

This heady-sounding technology caught my attention, and I was soon seated across from Azeez Bhavnagarwala, Metis’ founder and CEO, at the recent SEMICON West to learn more.
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Note: You may wonder why the ESD Alliance, a SEMI Technology Community, chose to sponsor “Supply Chain Verification –– Critical Enabler for Next-Generation MedTech Innovations.” I explain why in the blog post below that first appeared earlier this week on Semiwiki. We hope to see you there and at our Wednesday evening reception. Details are in the blog.

Chip design verification has long been a key component of any design project developing silicon intended to go into manufacturing. As designs become more complex, so does the manufacturing risk, and the focus on thorough verification becomes ever more critical.

Another dimension of complexity coming into play and considered throughout the entire electronic system. The shift toward chiplet-based design, 3D-IC and other innovative packaging technologies are driving the need for verification beyond the individual chip. System design verification that spans multiple devices, subsystems and even software code is becoming the norm for ensuring that an electronic system can be manufactured and perform as intended.
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Just across the street from this year’s DAC is SEMICON West and, like DAC, it has a wealth of programs, including a new Sustainability Summit, a market symposium, a test vision symposium and TechTalks. A Workforce Development Pavilion will address the needs of job seekers and talent professionals.

It will also feature an ESD Alliance-sponsored panel. “Supply Chain Verification –– Critical Enabler for Next-Generation MedTech Innovations” will be held in the Smart MedTech Meet the Experts Stage at Exhibition Level, Room 2, Moscone Center South Hall.

The panel scheduled for Tuesday, July 12, from 11:35 a.m. until 12:25 p.m., will underscore system verification challenges and opportunities that impact the entire electronic product design and manufacturing supply chain. Thought leaders and experts will discuss the slowdown of Moore’s Law and the trend toward specialized packaging, tailored chips and their diverse applications, and ways in which verification across the supply chain can be improved.

Lucio Lanza, Managing Partner of Lanza techVentures, will serve as moderator. The panel will consist of experts in chip design verification including Mike Chin, Principal Software Engineer at Intel; Lu Dai, Senior Director of Engineering from Qualcomm and Chairman of Accellera; and Dave Kelf, Breker Verification Systems’ CEO. Jan Vardaman, President of TechSearch International, is an expert in manufacturing and packaging.
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Maheen Hamid is a recognized entrepreneur in our community and co-founder along with her husband Adnan of Breker Verification Systems, a chip design verification company. Maheen’s role at Breker is COO and CFO. She is also a mother of two, a 16-year-old daughter and a son who is eight. Despite what must be a heavy workload and juggling act, she is an active member and a welcome voice on the ESD Alliance’s Governing Council.

In addition, Maheen was recently named one of Silicon Valley’s 100 most influential women by Silicon Valley Business Journal, selected for her financial experience in deal structuring and operations management for small- to medium-sized businesses. Her strong commitment to entrepreneurship as the way to bring broader change is a valuable trait and a topic we discussed during a recent conversation.

Maheen and the other recipients of the Silicon Valley’s 100 most influential women will be honored at an awards ceremony Thursday, June 14, at Signia by Hilton in downtown San Jose, Calif.

Smith: Does the semiconductor industry offer a good career path for women?

Hamid: Over the years, it is becoming increasingly evident that the semiconductor industry provides the foundational fuel for the technological revolution of modern times. It is an exciting space rooted in fundamental science that enables innovation to propel humankind forward. In addition to the technical challenges to be solved by some of the best and brightest engineers, scientists and technologists, competitive pressures and market dynamics also create interesting career paths in the business and management tracks.

Per a 2020 study by GSA and Accenture, gender diversity in the industry remains low, with women comprising about 25% of the entire workforce and less than 10% as roles progress towards management and board level roles. Larger companies have been performing better in recruiting and retaining women.

However, studies can only show trends but they do not define the breadth of opportunities available. As companies weather economic ups and downs, focus shifts toward retaining the sharpest problem-solving skills, regardless of the gender behind it or the field of application. Women are naturally tenacious and creative about holistic problem solving. Combine that with the growing confidence that we are capable of achieving extraordinary heights, there is much to be gained by pursuing a career in the semiconductor industry.

A small sidebar and a fun fact: Breker Verification Systems is the company I co-founded with Adnan, who has an extraordinary engineering mind in the field of verification. We brought to market leading-edge technologies that push the boundaries of verification methodologies and achievable coverage. I find it incredible that it is computer language pioneer Dr. Grace Hopper who coined the terms “bug” and “debugging” when she had to remove moths from an early computer her team was working on!

Fun Fact: Breker boasts an engineering workforce that is greater than 50% women!!
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My interview series continues with a far-reaching and fascinating conversation I had with Laurie Balch of Pedestal Research and a member of the ESD Alliance. Laurie is a great resource and I’m pleased she took the time to talk with me.

As a leading analyst covering the electronic system design segment, Laurie Balch is well steeped in identifying and analyzing technology trends and forecasting new market opportunities. She’s also a great resource for a company’s strategic planning, mergers and acquisitions and market insights and development, which is why I looked forward to our recent discussion.

Industry longtimers remember Laurie from Dataquest, then Gary Smith EDA when she and other senior analysts joined the late Gary Smith at his market intelligence and advisory services firm. Laurie is now President and Research Director at Pedestal Research, a market research firm for the design and engineering industries. Pedestal Research, a member of the ESD Alliance, was founded in 2018 when it took over the business operations of Gary Smith EDA.
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Avery is noted for functional verification solutions and SystemVerilog/UVM Verification IP, system-level virtual platform co-simulation and hardware-assisted verification, and gate-level simulation sign-off solutions for SoC verification. Its Vice President of Worldwide Sales and Marketing Chris Browy and I discussed a range of functional verification topics a while back. A condensed version of our talk appears in a blog post on the SEMI website.

Chris Browy, Vice President of Worldwide Sales and Marketing of Avery Design Systems, is a go-to expert on all things functional verification.

Avery, a well-established provider of functional verification solutions, has been around since 1998 supporting a growing and complementary line of SystemVerilog/UVM Verification IP, system-level virtual platform co-simulation and hardware-assisted verification, and gate-level simulation sign-off solutions for system-on-chip (SoC) verification. It is also a member of the ESD Alliance, a SEMI Technology Community.

I recently caught up with Browy and asked him how an engineer verifies and ensures the compliance of new chip designs with emerging standards when there is no proven system platform yet to support those standards. His informed response kicked off our conversation.

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Not long ago, Cadence’s Chin-Chi Teng and I had a fascinating discussion about how ML is reshaping EDA and the semiconductor industry, the cloud’s role in the evolution of ML in design and its impact on Moore’s Law. 

The post is a good look at Cadence’s leadership at the technological forefront in incorporating ML techniques in its chip design products. It’s a great reminder as well that Cadence’s President and CEO Dr. Anirudh Devgan will be honored with the 2021 Phil Kaufman Award for Distinguished Contributions to Electronic System Design at an award ceremony and banquet Thursday, May 12.

I hope you’ll join us in honoring Anirudh. Registration details can be found on the 2021 Phil Kaufman Award ceremony and banquet page.

Machine learning (ML) and artificial intelligence (AI) have ushered in tremendous opportunities for faster growth, problem-solving and technological development in the electronic system design ecosystem. Cadence Design Systems, Inc., a member of the ESD Alliance, a SEMI Technology Community, is at the technological forefront in incorporating ML techniques in its chip design products.

I spoke with Chin-Chi Teng, Senior Vice President and General Manager of Cadence’s Digital & Signoff Group, about how ML is reshaping EDA and the semiconductor industry, the cloud’s role in the evolution of ML in design and its impact on Moore’s Law. Teng also offers advice on how engineering students can calibrate their education to prepare to work with this transformative technology and urges them to have fun in the process.

Smith: How is ML changing the EDA industry?

Teng: ML is changing EDA for the better in many ways. It’s more difficult than ever to design chips, and ML is helping by overcoming the complexity, size and technology interdependencies. At the same time, ML is helping our own engineers solve certain classes of EDA algorithm, tool, and flow/solution challenges so that we can deliver even better EDA tools to our user base.
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