Electronic Design Automation (EDA) is essential for the entire semiconductor design-to-manufacturing process. EDA tools streamline the design process, speed up development cycles, and ensure higher precision in chip design. Accellera Systems Initiative is an independent standards body that members of the Electronic System Design (ESD) Alliance rely on for its focus on system-level design, modeling and verification standards used extensively throughout the Electronic Design Automation (EDA) ecosystem.

Bob Smith, Executive Director of the ESD Alliance, recently talked with Lu Dai, Senior Director of Technical Standards at Qualcomm and Accellera’s Chair about its new and future standards, and its successful global Design Verification Conference (DVCon) events.

Smith: What’s new in Accellera’s standards effort since we last spoke?

Dai: We are working on two new initiatives. The first and biggest initiative is our recently formed Federated Simulation User Group. Our members requested an end-to-end simulation environment or models that can be plugged into a system-level simulation environment. This challenge triggered industry-wide discussions among Qualcomm, NXP and many other semiconductor companies, especially those from Europe tied to auto and avionics industries.

The need for this new standard effort is being driven by industries such as automotive where tiny microcontroller chips are traditionally used. The automotive industry has some existing simulation standards that include physical devices. With autonomous vehicles, systems on chips (SoCs) are replacing microcontrollers and handling system-level features that require rigorous system-level simulation. The user group is tasked with reviewing current automotive industry simulators and discovering how our traditional register transfer level (RTL) code- or emulation-based simulations could work with them via an interface.

This effort has attracted new companies outside of the traditional EDA world. Ford, for example, is now an Accellera member and has a seat on our board. It’s exciting to see this collaboration.

Functional safety is another initiative that we started a few years ago, also driven by the advancements in autonomous vehicles. Accellera’s focus is to define functional safety as a format that can be carried through the design stages from intellectual property (IP) to SoC, and from front-end design to back-end. Across the different stages of design and verification, an engineer can then confirm that the functional safety goal is maintained. We’ve published resources including whitepapers and are currently working on developing the language format.

Smith: Where do you see Accellera’s next standards efforts?

Dai: We have a mixed-signal standard coming out soon. It adds a mixed-signal interface to the SystemVerilog standard, currently under IEEE management because Accellera donated it to IEEE.

A common question we’re asked is, “What are you doing with AI?” Accellera is a heavily EDA-centric standards body, and EDA tools are increasingly incorporating AI. AI consumes and outputs large amounts of data. A challenge is how to ensure the AI work output from one vendor’s EDA tool can propagate to another EDA tool.

Accellera may look at defining an AI data format for EDA. It comes with a unique challenge because AI data is highly proprietary, both from the vendor’s and customer’s perspectives, so a robust security solution is needed. We may need to consider an interface standard, because companies may not be willing to share data, even with other groups that are in the same company. among their partners. They might need to hide the data and have a special interface to extract the data that they are willing to share. Accellera could investigate how to make AI deployment cross-vendor while allowing vendors and customers to protect their IP.

Another area for potential new standards is around supply chain security challenges. This is a global issue driven in part by the COVID experience and geopolitical concerns. One possible approach is to use tagging. When a chip comes out of the fab, it would have a tag designating where it was designed and manufactured, and where the tooling is from. The tag would also include data about the regions or countries the design traveled through during the entire flow from design to manufacturing.

Smith: Is Accellera looking into any standards or addressing any open-source design and verification flows?

Lu: Accellera has been in the open-source domain for quite some time. Accellera has a language reference manual, user guides and reference implementations. Because many Accellera standards are related to language, we often work on libraries when a new language comes out and reference implementations to help our community deploy that standard. Reference implementation libraries are open source, as is our SystemC material. We have an active open-source SystemC community.

Smith: I hear that the DVCon conferences are expanding globally. What’s driving that?

Dai: Engineers enjoy attending conferences in person where they can reconnect with peers, build new connections and foster collaboration. We have regional DVCon events to bring information to our community and make Accellera more accessible to them. We now host several DVCon conferences in North America, Europe and Asia. Our next DVCon will be held in San Jose, Calif., from Feb. 24-27.

Smith: How can readers of this blog post get more information about Accellera?

Dai: For up-to-date information about Accellera’s activities, please visit our website:  https://accellera.org/.

Lu Dai is Senior Director of Technical Standards at Qualcom and is a leader in semiconductor standards and industry organizations including Accellera. Dai holds a Master of Science degree in Electrical Engineering from Cornell, and a Bachelor of Science degree in Electrical Engineering and Computer Science from UC Berkeley.