As chiplets start to catch on throughout the chip designer community, security is a growing concern. That’s why the ESD Alliance, a SEMI Technology Community, and member company Silicon Assurance are hosting a panel discussion webinar to emphasize the emerging security threats during chiplet design, assembly and testing. It will be held Thursday, March 14, from 9 a.m. until 10 a.m.
The panel led by Raj Gautam Dutta, CEO of Silicon Assurance, a startup addressing security assurance and trust issues in silicon chips, will identify threats that occur at the different stages of chiplet design, assembly and test. He and his panelists will examine the latest advancements and discuss safeguarding the future of chiplet technology.
