When I last talked with Rick Eram, Excellicon’s vice president of sales and operations, we discussed how to manage timing challenges early in the design cycle, otherwise known as a “shift-left” methodology. (See SEMI blog post titled Excellicon – Managing Critical Timing Constraints Across Design and Verification to Reduce Timing).

As a provider of design tools that connect early design specifications to their physical representations, Excellicon is paving the way to optimally partition structures and floorplans. In a follow-up conversation, Rick offered more of his perceptions on the advantages of early design techniques. What follows is a condensed version of our conversation.

Smith: How do you define “Implementation-ready register transfer level (RTL) code,” a term that seems to be used more regularly with chip designers?

Eram: The issues and challenges are always discovered in the backend; in many cases the RTL was not properly or suitably coded for physical implementation.

Generally, during the RTL development stage, the focus is on the functionality and correctness of the RTL code. Designing RTL code that is suitable for physical design and for easier timing closure has not been a concern.
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