Happy New Year and good wishes for a prosperous 2023!

Our events season begins with the 2022 Phil Kaufman Award Ceremony and Dinner honoring Dr. Giovanni De Micheli Thursday, February 23, at 6:30pm in San Jose. We co-host the evening with the other award sponsor the IEEE Council on Electronic Design Automation (CEDA).

The event will be held at The GlassHouse in San Jose, Calif. Early bird ticket pricing for the evening is available through next Friday –– January 13 –– at $175 per individual from member companies and $225 each for non-members. After January 13, member tickets are $225 each and $275 per non-member. Member pricing is offered for individuals or companies that are active SEMI or IEEE members.

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Why not register now for the 2022 Phil Kaufman Award ceremony and banquet honoring Dr. Giovanni De Micheli to take advantage of early-bird pricing? It’s Thursday, February 23, 2023, from 6:30 p.m. until 9:30 p.m. at The GlassHouse, 2 South Market Street in San Jose, Calif.,

The evening, certain to be enjoyable and memorable, will be hosted by the ESD Alliance and the IEEE CEDA to honor Dr. De Micheli, a true force in the EDA community.

Early bird ticket pricing is available now through Friday, January 13, at $175 per individual from member companies and $225 each for non-members. After January 13, member tickets are $225 each and $275 per non-member. Member pricing is offered for individuals or companies that are active SEMI or IEEE members

Join us as we acknowledge Dr. De Micheli’s extensive contributions our community. According to Aart de Geus, Chairman and CEO of Synopsys: “Professor De Micheli, or Nanni to many of us who’ve been driving our industry forward for decades, stands as a relentless advocate for our field. While many predicted our industry was fully matured, he remained focused and creative, be it with the encoding of finite-state machines combined with logic minimization or solving the cell-library mapping problem with Boolean matching. I am not alone when I express my appreciation to Nanni for advancing the field, but most important, for continuing to add findings that keep our profession fresh and exciting!”

Registration is open, so register today!

When I last talked with Rick Eram, Excellicon’s vice president of sales and operations, we discussed how to manage timing challenges early in the design cycle, otherwise known as a “shift-left” methodology. (See SEMI blog post titled Excellicon – Managing Critical Timing Constraints Across Design and Verification to Reduce Timing).

As a provider of design tools that connect early design specifications to their physical representations, Excellicon is paving the way to optimally partition structures and floorplans. In a follow-up conversation, Rick offered more of his perceptions on the advantages of early design techniques. What follows is a condensed version of our conversation.

Smith: How do you define “Implementation-ready register transfer level (RTL) code,” a term that seems to be used more regularly with chip designers?

Eram: The issues and challenges are always discovered in the backend; in many cases the RTL was not properly or suitably coded for physical implementation.

Generally, during the RTL development stage, the focus is on the functionality and correctness of the RTL code. Designing RTL code that is suitable for physical design and for easier timing closure has not been a concern.
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