Note: Below is a Q&A post I did initially for SEMI’s blog with Thiago Figueiro, vice president of Sales, Marketing and Business Development at Aselta. Aselta produces software for wafer and mask patterning based on e-beam technology for IC manufacturing, along with advanced metrology solutions for scanning electron microscopes. Our wide-ranging conversation covered trends and improvements in semiconductor manufacturing, supply chain challenges and the startup experience in France.

Aselta Nanographics of Grenoble, France, which produces software for wafer and mask patterning based on e-beam technology for IC manufacturing, along with advanced metrology solutions for scanning electron microscopes, recently became an ESD Alliance member. Adding to its impressive credentials, Aselta is a spin-off of CEA-Leti, the electronics and information technologies research institute also in Grenoble.

The increasing complexity of IC manufacturing poses a number of challenges including the mask data preparation required to enable technology improvements such as multi-beam (MB) mask writers and extreme ultraviolet (EUV) lithography. Measuring and inspecting the effects both on reticle and on wafer are also challenging.

I recently spoke with Thiago Figueiro, vice president of Sales, Marketing and Business Development at Aselta, to learn more about these issues. Our wide-ranging conversation covered trends and improvements in semiconductor manufacturing, supply chain challenges and the startup experience in France.

Smith: What trends are you seeing in semiconductor manufacturing?

Figueiro: Several technology nodes are becoming critical for different reasons, especially as the IC shortage lasts through at least 2023 depending on how and when the supply chain improves. Investments in older technology nodes are expanding production volumes in 200mm wafer fabs and for 300mm legacy nodes, opening new opportunities to increase supply by leveraging older and existing fabs.

Increasing stochastic effects are also becoming a bigger concern for advanced nodes and are particularly important in EUV lithography since random variations increase local CD dimension variability. This roughness impacts the electrical performance of devices and increases the risk of failures.

A contour extraction over multi-layer image and an analysis of the extraction quality. Source: Aselta Nanographics

And finally, semiconductor manufacturing is investing heavily in using all available data and generating more of it for better inline decision making. Practices such as using artificial intelligence (AI) for identifying and classifying weak signals, exploring big data to identify root causes of production issues, and monitoring and relying on digital twins to anticipate issues and test reliability are also rising in adoption. Developing techniques to both better explore and produce data without increasing production flow length is critical to taking full advantage of these trends.

Smith: How has wafer and mask patterning changed over the years?

Figueiro: Wafer and mask patterning have always required expertise and they’re getting even more complex. For instance, EUV is being adopted for advanced nodes for both logic and memory (DRAM). Inverse lithography technology (ILT) is a method that starts with patterns that are intended to be realized on the wafer and then generates the desired mask patterns that will produce the desired patterns on the wafer. Usually, those patterns are highly complex because they are often curvilinear shapes. The most sophisticated masks for advanced nodes are likely to use multi-beam mask (MB) writers for producing such ILT patterns.

Mask patterning is now also performed using MB mask writers, and the total number of masks produced with MB technology is increasing for advanced nodes. MB tools for mask writing are a plus for EUV and mandatory for high numerical aperture (NA) EUV technology nodes. Variable-shaped beam (VSB) is not being replaced, but what we are seeing is a co-existence of MB, VSB and laser writers.

An assessment of the pattern fidelity based on the scoring. Source: Aselta Nanographics

Coincidentally, mask proximity correction (MPC) solutions are now more widely used to improve mask pattern fidelity for advanced nodes. The MPC flow relies on model-based estimation of potential issues in the mask writing process. Adjusting the exposure dose or the geometry of each pattern helps compensate for these issues. Almost all critical masks for nodes 14nm and below rely on some MPC technology flow.

Smith: What kinds of technology improvements should we expect to see in 2022?

Figueiro: We see some interesting developments. Contour-based metrology is growing in adoption. Scanning electron microscopy (SEM)-augmented metrology needs are increasing for advanced nodes, requiring patterning control over in-die 2D complex structures such as edge placement errors, roughness and 3D profiles.

We expect to see announcements about new solutions for metrology and process control relying on e-beam technology, such as critical dimension-scanning electron microscopes (CD-SEMs), multi-beam SEMs and e-beam inspection tools. Finally, collecting more information from various steps in patterning will help drive improvements in mask and wafer proximity correction and may help optimize the entire patterning. This could be big news in 2022.

Smith: Have the supply chain challenges affected the semiconductor business in Europe?

Figueiro: The automotive industry is heavily impacted by the chip supply shortage, deepening Europe’s concerns about its chip dependency. To counter this, Europe has announced investments to increase domestic chip manufacturing volumes. For example, GlobalFoundries in Dresden, Germany and STMicroelectronics in Grenoble are investing more than $1 billion to expand their fabs. Intel recently announced a new fab in Germany and investments in France and Italy as well.

Smith: Is there a support network for semiconductor industry entrepreneurs in France?

Figueiro: The French government provides a series of incentives for startups and is working to position itself as a start-up nation with a record number of French unicorns and startup investments in 2021. One important incentive is the CIR (research tax credit) provided by the government for companies investing heavily in the development of new technology.

CEA-Leti is an important player in the French and European ecosystem for creating strategic partnerships that help nurture startups. Aledia, Aselta and Soitec are good examples of the value of creating such partnerships in the semiconductor domain.

About Thiago Figueiro

Thiago Figueiro has deep technical knowledge in mask data preparation and geometrical metrology and leverages his business knowledge to build bridges between users and Aselta’s technical teams. He is a computer engineer with a M.Sc. in semiconductors and a solid understanding of how to bring practical EDA solutions to market. Figueiro holds a Ph.D. in microelectronics from Grenoble Alpes University and an Executive MBA from école de Management de Lyon.