Note: I turn this week’s Bridging the Frontier blog over to Anirudh Devgan, President and CEO, Cadence Design Systems and ESD Alliance Governing Council Member, to give us his view of Computational Software. His viewpoint first appeared in the ESD Alliance newsletter distributed at SEMICON West/DAC. It’s now available on the ESD Alliance website.

I truly believe this is the golden era of semiconductors. Nearly everything in our lives is becoming digital and everything digital requires semiconductors. Today, the industry is about $500B and is on the path to $1T in the next few years. The overall semiconductor industry has always been cyclical, but I believe it is becoming less so, in fact, it is rapidly becoming a fundamental growth industry.

The generation and processing of data, especially unstructured data, is impacting everything from device compute, to the edge and to the cloud. It is transformational in many ways and has led to the emergence of data-driven algorithms and AI semiconductor compute. The motivation is to process the unstructured data and get intelligence out of it. Technology innovations are enabling waves of new products for many applications such as automotive, mobile, manufacturing, healthcare and even the rise of the metaverse. This fundamental trend will continue for decades, and it’s a thrill to be in the middle of it all.

Another growth driver is systems companies’ in-house semiconductor development to optimize the application architectures to maximize performance, address power efficiencies and improve the safety and security of their end products, plus the added benefit of increased control of their supply chain. Also emerging is a new era of system in a package (SiP) and the creation of chiplets. As Moore’s law matures, this will provide a massive improvement in system performance while focusing on the compute portion that benefits most from new process node technologies. EDA must provide an integrated platform to design and analyze all the aspects of SiP and chiplets, which is quite a challenge, with Die-to-Die IP playing a critical role. Overall these enable designers to combine the benefits of advanced semiconductor node innovation with other architectural changes to increase data processing throughput within power and form factor constraints. (more…)

Note: As SEMICON West and DAC wind down this week, let’s have a look at a Q&A blog post I did on Metis Microsystems, a member of the ESD Alliance, that appeared on the SEMI Website.

Any chip design group with a project specification that prioritizes improved energy efficiency and performance may want to learn more about Metis Microsystems, a member of the ESD Alliance, a SEMI Technology Community.

This East Coast startup founded in 2017 develops advanced CMOS Memory and Arithmetic component intellectual property (IP) to improve energy efficiency and performance of processors. Metis’ circuit IP harvests a device’s transient data to alleviate circuit limits on CMOS scaling. Applications for the technology are relevant to semiconductor markets limited by compute performance and energy efficiency.

This heady-sounding technology caught my attention, and I was soon seated across from Azeez Bhavnagarwala, Metis’ founder and CEO, at the recent SEMICON West to learn more.
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Note: You may wonder why the ESD Alliance, a SEMI Technology Community, chose to sponsor “Supply Chain Verification –– Critical Enabler for Next-Generation MedTech Innovations.” I explain why in the blog post below that first appeared earlier this week on Semiwiki. We hope to see you there and at our Wednesday evening reception. Details are in the blog.

Chip design verification has long been a key component of any design project developing silicon intended to go into manufacturing. As designs become more complex, so does the manufacturing risk, and the focus on thorough verification becomes ever more critical.

Another dimension of complexity coming into play and considered throughout the entire electronic system. The shift toward chiplet-based design, 3D-IC and other innovative packaging technologies are driving the need for verification beyond the individual chip. System design verification that spans multiple devices, subsystems and even software code is becoming the norm for ensuring that an electronic system can be manufactured and perform as intended.
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