Avery is noted for functional verification solutions and SystemVerilog/UVM Verification IP, system-level virtual platform co-simulation and hardware-assisted verification, and gate-level simulation sign-off solutions for SoC verification. Its Vice President of Worldwide Sales and Marketing Chris Browy and I discussed a range of functional verification topics a while back. A condensed version of our talk appears in a blog post on the SEMI website.
Chris Browy, Vice President of Worldwide Sales and Marketing of Avery Design Systems, is a go-to expert on all things functional verification.
Avery, a well-established provider of functional verification solutions, has been around since 1998 supporting a growing and complementary line of SystemVerilog/UVM Verification IP, system-level virtual platform co-simulation and hardware-assisted verification, and gate-level simulation sign-off solutions for system-on-chip (SoC) verification. It is also a member of the ESD Alliance, a SEMI Technology Community.
I recently caught up with Browy and asked him how an engineer verifies and ensures the compliance of new chip designs with emerging standards when there is no proven system platform yet to support those standards. His informed response kicked off our conversation.
