If you had trouble settling into working from home last year, you are not alone. Now try to imagine how our engineering community managed a collective set of challenges as they attempted complex chip innovation from their home offices. Yes, I know –– daunting.
And so, I invite you to attend a panel that shines a light on the chip design and verification project upheaval caused by the pandemic. Set aside an hour Wednesday, June 9, to join us for a lesson on overcoming the perils of chip design at home. It will be populated by chip design and verification engineers accustomed to robust software and hardware resources readily available at their physical office.
This panel is co-hosted by two stalwarts of the electronic system design ecosystem –– the ESD Alliance and Accellera, a long-overdue industry first that I expect will not be the last. The ESD Alliance and SEMI, where we are a Technology Community, welcome the partnership. 
As our panelists will attest, work from home, WFH, remote work or whatever you call this last year changed our routines and our lives, possibly forever. Design and verification didn’t stop even though our panelists had to work through hits to their complicated flows and project cycles due to VPN tool and system access, Zoom-based collaboration and everyday home interruptions.
