Note:  ES Design West, a co-located even at SEMICON West, continues today. Our final “Meet the Experts” session on Advanced Applications starts at 1:30 p.m. “Holistic Cost of Design” will be presented by Balachandran (Bala, for short) Rajendran, CTO, EDA at Dell EMC, the data storage giant, at 2:35 p.m. He and I recently talked about his views on efficient design flows.

On the surface, efficient chip design infrastructures doesn’t sound all that compelling as a topic. Until you talk with Bala. Bala is an engineer to the core, and on a campaign to efficiently reorganize engineering groups in a more holistic fashion backed by his 22+ years of experience in various roles in CAD, Infrastructure and IT. 

According to Bala, the cost of design and manufacturing is increasing drastically in the push to accelerate innovation. He goes on to say that the cost of design in newer technology nodes is twice the previous node, even though R&D efficiency is greater in the Semiconductor Industry.

The accelerated costs of design and manufacturing are due in large measure to added features in an SoC design that could impact size, power and performance, all of which means more design work and time. Of course, design, verification, software, IT, CAD and infrastructure groups continually optimize their environment in a move to make it more efficient and push it to the edge. They implement features and applications to improve the design and verification flow. All told, this well-intentioned practice is impacting design features and design quality. Modularity prevents progress.

One other factor that influences the overall environment is human resources, adds Bala. Often, a company that needs to get a design out faster will add headcount without recognizing that other factors should be considered as well. It’s less efficient and, remarkably, happens all the time.
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