Now that SEMICON West is over, that summer vacation you dream of is closer than ever.

Before you head off to the beach, mountains or somewhere exotic, have a look at the photos of the keynote session and talks that were part of ES Design West, a first-time co-located event at SEMICON West.

ES Design West included a robust program of six Meet the Experts sessions with a total of 26 presentations and a techTalk session that had two speakers and a panel. Additionally, 22 exhibitors took the leap and helped pioneer the first ES Design West. Presentations will be available to ES Design West attendees.

A special nod to IBM who brought its IBM Q quantum computer to ES Design West showcasing quantum computing architecture built upon decades of semiconductor industry advances. Attendees saw demos of how the IBM Q Experience quantum cloud services platform and Qiskit, an open source quantum software framework, are used to program and experiment with real IBM Q systems.

Below are a set of photos from SEMICON West and ES Design West that captured the mood and enthusiasm that dominated the week in San Francisco. They were taken by Paul Cohen, senior manager of the ESD Alliance at SEMI.
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Note:  ES Design West, a co-located even at SEMICON West, continues today. Our final “Meet the Experts” session on Advanced Applications starts at 1:30 p.m. “Holistic Cost of Design” will be presented by Balachandran (Bala, for short) Rajendran, CTO, EDA at Dell EMC, the data storage giant, at 2:35 p.m. He and I recently talked about his views on efficient design flows.

On the surface, efficient chip design infrastructures doesn’t sound all that compelling as a topic. Until you talk with Bala. Bala is an engineer to the core, and on a campaign to efficiently reorganize engineering groups in a more holistic fashion backed by his 22+ years of experience in various roles in CAD, Infrastructure and IT. 

According to Bala, the cost of design and manufacturing is increasing drastically in the push to accelerate innovation. He goes on to say that the cost of design in newer technology nodes is twice the previous node, even though R&D efficiency is greater in the Semiconductor Industry.

The accelerated costs of design and manufacturing are due in large measure to added features in an SoC design that could impact size, power and performance, all of which means more design work and time. Of course, design, verification, software, IT, CAD and infrastructure groups continually optimize their environment in a move to make it more efficient and push it to the edge. They implement features and applications to improve the design and verification flow. All told, this well-intentioned practice is impacting design features and design quality. Modularity prevents progress.

One other factor that influences the overall environment is human resources, adds Bala. Often, a company that needs to get a design out faster will add headcount without recognizing that other factors should be considered as well. It’s less efficient and, remarkably, happens all the time.
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It’s a pleasure to welcome you to ES Design West and SEMICON West on behalf of the ESD Alliance, a SEMI Strategic Association Partner!

The ES Design West goal is to enable and accelerate conversations, information exchange and collaboration to address common issues, challenges and opportunities that move new electronic products from concept to consumer. We invite you to help us meet that goal as we proudly highlight commercial achievements of electronic system design, including IP, EDA, embedded software, design services and infrastructure including design in the cloud through an assortment of presentations and panel discussions.

As you walk the exhibit floor, meet colleagues and friends, and hear keynote speakers and other presenters, expect to talk about the growing links between electronic system and semiconductor design with the electronic product manufacturing and supply chain. It’s happening and it’s real.
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