Yasushi Ozaki, Director of Engineering Department overseeing product design and Development, at Renesas, spoke at the Atrenta Technology Forum First inYokohama.  This is Tech-On’s coverage of his presentation and his evaluation of SpyGlass Physical, which is an EDA tool for estimating chip area and logic depth at the RTL stage:

http://www.nikkeibp.co.jp/article/news/20120720/316569/

Lee PR does work for Atrenta