Posts Tagged ‘IEEE’
Thursday, March 29th, 2012
This event is happening next week! Worth signing up if you can get down
there!………
EDPS is coming up again! It’ll be held April 5-6, 2012 at the Monterey Beach Hotel in Monterey California.
This year, the 3D topic will be the focus of day two.
First and foremost, Riko Radojcic, director of engineering at Qualcomm, will be talking about the 3D IC roadmap as the keynote speaker on day two. (see his views on 3D standards: http://www10.edacafe.com/blogs/ed-lee/2011/04/11/riko-radojcic-on-3d-standards/
Following the 1-hour keynote will be four 1/2 hour talks on various specific 3D-related topics:
* Stephen Pateras of Mentor on BIST for 3D ICs
* Arif Rahman of Altera on FPGA design challenges, presumably 3D ones
* Marc Greenberg of Cadence on the wide-IO standard for putting memory stacks on processors
* Sandeep Goel of TSMC and Bassilios Petrakis of Cadence on an end-to-end test flow for 3D IC stacks
Then there’s a lunch panel on 3D, moderated by Steve Leibson of Cadence, with these panelists addressing: The short-, medium and long-term path to the 3D Ecosystem.
* Herb Reiter
* Samta Bansal of Cadence
* Dusan Petranovic of Mentor
* Deepak Sekar of Monolithic 3D
* Steve Smith of Synopsys
* Phil Marcoux of PPM Associates
Herb is arguably the primary 3D observer and advocate on what technologies have to be in place to handle the upcoming 3D challenge that’s starting to hit designers now.
John Swan is the General Chair of EDPS 2012. Herb Reiter is the Session Chair for the keynote, four shorter presentations and the panel discussion during “3D Day”, Friday, April 6.
Very worthwhile to attend if you can get the time off.
Tags: 3D, 3D Ecosystem, 3D IC, Altera, Arif Rahman, Cadence, Chip Design, chip designers, DAC, Deepak Sekar, Dusan Petranovic, EDA, eda 2 asic Consulting, EDPS, Electronic Design Automation, Electronic Design Process Symposium, Herb Reiter, IEEE, John Swan, Marc Greenberg, Mentor, Monolithic 3D, Phil Marcoux, PPM Associates, Riko Radojcic, Samta Bansal, Sandeep Goel, semiconductors, Stephen Pateras, Steve Leibson, Synopsys, TSMC
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Thursday, March 22nd, 2012
EDPS is coming up again! It’ll be held April 5-6, 2012 at the Monterey Beach Hotel in Monterey California.
This year, the 3D topic will be the focus of day two.
First and foremost, Riko Radojcic, director of engineering at Qualcomm, will be talking about the 3D IC roadmap as the keynote speaker on day two. (see his views on 3D standards: http://www10.edacafe.com/blogs/ed-lee/2011/04/11/riko-radojcic-on-3d-standards/
Following the 1-hour keynote will be four 1/2 hour talks on various specific 3D-related topics:
* Stephen Pateras of Mentor on BIST for 3D ICs
* Arif Rahman of Altera on FPGA design challenges, presumably 3D ones
* Marc Greenberg of Cadence on the wide-IO standard for putting memory stacks on processors
* Sandeep Goel of TSMC and Bassilios Petrakis of Cadence on an end-to-end test flow for 3D IC stacks
Then there’s a lunch panel on 3D, moderated by Steve Leibson of Cadence, with these panelists addressing: The short-, medium and long-term path to the 3D Ecosystem.
* Herb Reiter
* Samta Bansal of Cadence
* Dusan Petranovic of Mentor
* Deepak Sekar of Monolithic 3D
* Steve Smith of Synopsys
* Phil Marcoux of PPM Associates
Herb is arguably the primary 3D observer and advocate on what technologies have to be in place to handle the upcoming 3D challenge that’s starting to hit designers now.
John Swan is the General Chair of EDPS 2012. Herb Reiter is the Session Chair for the keynote, four shorter presentations and the panel discussion during “3D Day”, Friday, April 6.
Very worthwhile to attend if you can get the time off.
Tags: 3D, 3D Ecosystem, 3D IC, Altera, Arif Rahman, Cadence, Chip Design, chip designers, DAC, Deepak Sekar, Dusan Petranovic, EDA, eda 2 asic Consulting, EDPS, Electronic Design Automation, Electronic Design Process Symposium, Herb Reiter, IEEE, John Swan, Marc Greenberg, Mentor, Monolithic 3D, Phil Marcoux, PPM Associates, Riko Radojcic, Samta Bansal, Sandeep Goel, semiconductors, Stephen Pateras, Steve Leibson, Synopsys, TSMC
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Thursday, January 12th, 2012
This year, we’ll see an old standards battle get resolved. Now that all the players are participating in the IEEE Standard 1801 project (IEEE Standard for Design and Verification of Low Power Integrated Circuits), we can finally put the UPF-CPF debate to rest. Let’s hope that peace will reign and the temptation to fight one more time about a single low power standard will be overcome.
Social media will become less of a curiosity or a perceived waste of time for engineers. We’ll see more EDA customers helping answer each other’s questions and sharing more information (nothing proprietary, of course). LinkedIn discussions will have more depth, not simply people posting “read my blog”.
Facebook will remain more of a social vehicle, and for many engineers of our generation, a misunderstood channel. YouTube videos that provide good content – “how-to” and learning opportunities – will become popular. Twitter will remain a mystery for most, while a minority will find it of much value (include me in the minority). Marketers who spam social media channels with marketing-speak will be shunned. And, we’ll have some great guests on Conversation Central radio.
Karen Bartleson
Sr. Director, Community Marketing
Synopsys, Inc.
@karenbartleson
www.synopsys.com/blogs/thestandardsgame
President-Elect, IEEE Standards Association
Tags: @karenbartleson, 2012, Conversation Central radio, CPF, DAC, Design Automation Conference, EDA, EDA & IP, Electronic Design Automation, Facebook, IEEE, IEEE Standard 1801, IEEE Standards Association, IP, Lee PR, LinkedIn, Low Power ICs, Semiconductor IP, semiconductors, social media, Standards, Synopsys, Twitter, UPF, www.leepr.com, YouTube
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