What's PR got to do with it? 
Ed Lee
Ed Lee has been around EDA since before it was called EDA. He cut his teeth doing Public Relations with Valid, Cadence, Mentor, ECAD, VLSI, AMI and a host of others. And he has introduced more than three dozen EDA startups, ranging from the first commercial IP company to the latest statistical … More » Predictions 2014 – Atrenta’s Robert Beanland on SoC Integration for 2014February 3rd, 2014 by Ed Lee
“Ahhh, the age old question of, ‘What does EDA and IP need to do this year?’ Well, … The IP folks need a way to provide fully validated IP to their customers with not only a good understanding of all the validation that has been done, but also the expected use model and configurations for the IP. The use model is critical because it is quite common for IP to be ‘abused’ in a way or mode that the IP vendor never expected. When this happens, the customer must be able to assess the problem in-situ and work with the IP vendor to find a resolution. A standardized quality metric is much more desirable than the current option of comparing each vendor’s unique assessment of their validation. This validation and analysis should include, but is not limited to, power, clock domains, testability and physical. The ‘clean’ IP can then be used with more confidence by their customers in their SoC integration. The EDA folks need a way to allow SoC integrators an easy way to use the IP in a productive methodology which allows them to focus on the integration issues and not on the block level issues which take up valuable resources and time. This ‘intelligence’ of SoC integration must be shared between the integrators and the IP vendors in a way that is both elegant and efficient. Hopefully we can ride this year’s zodiac horse into the year of ‘more productive SoC design’.” Tags: Atrenta, Chip Design, EDA, EDA & IP, Electronic Design Automation, https://www.facebook.com/pages/Lee-Public-Relations/201964499825219?ref=hl, Intellectual property, IP, Lee PR, Lee Public Relations, RTL, Semiconductor IP, SoC, System on Chip, www.leepr.com One Response to “Predictions 2014 – Atrenta’s Robert Beanland on SoC Integration for 2014” |
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Interesting thought to the EDA industry on where to focus in 2014! As a first response, some answers kind of exist in pieces atleast I believe in the form of:
1. UVM sequences (reusable) for the IPs – can at times take care of “how to configure”
2. Assertions, of-course to deal with “misuse” at cycle accurate level – easier for standard protocols than custom ones
3. Scenario models that are emerging from EDA vendors such as Breker, Mentor, VayavyaLabs and others
4. UPF/CPF models at IP level, not sure how scalable/hierarchical it is yet (guess latest UPF does add some hierarchical capability)
Sure lot more is needed – especially on stitching the IP level sequences to SoC level – given that most of the low level driver/sequencer will disappear!
Good problem for 2014 once again, thanks for getting the focus set.
Srini