What's PR got to do with it? 
Ed Lee
Ed Lee has been around EDA since before it was called EDA. He cut his teeth doing Public Relations with Valid, Cadence, Mentor, ECAD, VLSI, AMI and a host of others. And he has introduced more than three dozen EDA startups, ranging from the first commercial IP company to the latest statistical … More » Who’s getting hit by the double whammy of verification?October 25th, 2012 by Ed Lee
 Piyush Sancheti In a recent article written by EDA industry watcher Ann Steffora Mutschler, Atrenta’s VP of Product Marketing Piyush Sancheti pointed to the curse of the verification double whammy for engineers: “For verification engineers and for designers, this is a double whammy,” noted Piyush Sancheti, vice president of product marketing at Atrenta. “If you ask a digital design or digital verification team, they will tell you that low-power design and the introduction of analog/mixed-signal components on what used to be a simple digital chip is a significant verification challenge. For verification engineers what this means is your finite state machines or your control logic just got that much more complicated. If you go from 2 domains to 20 domains, your verification complexity just increased an order of magnitude.” We caught up with Piyush in the Atrenta hallway and asked him to elaborate on his statement. Here’s what he said: Ed: So what is the double whammy and why should we care? Piyush: With the onset of A/MS and low power requirements, digital design teams now have to contend with two new foreign entries to their previous monolithic design environment. Ed: And they are…? Piyush: New logic blocks that are completely foreign to digital designers and the implementation of power management techniques like power & voltage domains. Voltage domains allow the timing critical portions of the design at a higher voltage (overdrive), and the rest at a lower voltage (underdrive). Power domains, on the other hand, allow one to turn off the power on entire blocks of the design when not in use. Ed: Haven’t digital designers always needed to be conscious and conscientious about power? Piyush: Not to the extent they must be these days. Here’s the challenge – say you are designing a chip for a smart phone. When you are watching a YouTube video, you don’t need the phone function, so you want to make sure that the phone functions are off. What’s the result? You’re saving power, or in consumer terms, preserving battery life. But, if the smart phone gets a call, you have to be sure the phone function turns on instantly, without adversely impacting your video viewing experience. So designers have to make sure the domains turn off and on in perfect harmony, almost like conducting a symphony. So what’s the problem? New power management logic that designers are not used to has been thrust on them rapidly and recently. They need to get up to speed fast. This is not an easy job. Not only that, but you now have very complex finite state machines that switch these functions on and off seamlessly. Ed: So what’s the solution? Piyush: A comprehensive methodology for functional and structural verification. Ed: Can you elaborate? Piyush: These complex finite state machines must be verified exhaustively for functional correctness. You need to make sure that the various functions on your smart phone wake up and shut off in a timely manner without adversely impacting the device behavior, and ultimately the user experience. With structural verification you need to make sure that the perimeter of the voltage and power domains are properly secured. When you have signals crossing one voltage domain to another, you need voltage level shifters. Similarly, you need isolation logic between power domains, to ensure that signals don’t float to unknown values when a domain is powered off. Ed: So what sort of tools and methodologies do you see out there to meet the double whammy challenge? Piyush: Well, of course, I’m most familiar with the Atrenta platform. There are undoubtedly other ways to go about this job. But from what I see, SpyGlass Power is being used by many large chip and system companies for static signoff of power and voltage domains. SpyGlass Advanced Lint enables exhaustive finite state machine verification using formal techniques. And with our recent acquisition of NextOp Software, we now have BugScope to ensure dynamic verification (simulation) is covering all the corner cases that are now part of your design because of this increased complexity. Ed: So your final words of wisdom? Piyush: Verification of modern day SoC designs is a daunting task. But like any complex problem a systematic approach using a combination of static and dynamic verification techniques will help you reach your device ambitions faster. – Note: Lee PR does work for Atrenta. Tags: A/MS, analog mixed-signal, Atrenta, Chip Design, EDA, Electronic Design Automation, finite state machines, Low-Power High-Performance Engineering Community, NextOP, semiconductors, SoC, SpyGlass, verification |
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