What's PR got to do with it? 
Ed Lee
Ed Lee has been around EDA since before it was called EDA. He cut his teeth doing Public Relations with Valid, Cadence, Mentor, ECAD, VLSI, AMI and a host of others. And he has introduced more than three dozen EDA startups, ranging from the first commercial IP company to the latest statistical … More » Powering up at DAC with Atrenta’s Kiran VittalMay 31st, 2012 by Ed Lee
Ed: So power, or rather more rigorous power management will be a hot topic at DAC. How come? What will be different this year? Kiran: As we all know, power is of the biggest concern to both mobile applications as well as wired devices. An average mobile SoC is over 100M gates operating at over 500Mhz and designers do everything necessary to apply all known power management techniques to reduce power. It will also be interesting to see that application processors for cloud-based servers are now being designed with over 10 power domains to shut off power in non operating regions and a quad core SoC consumes around 5 watts during maximum utilization and as little as 0.5 watts during idle time. Ed: So what approaches are we going to hear about @ DAC? Kiran: We are going to hear about power management, power intent creation using standards, power optimization, power verification and sign off. Ed: How do they stack up? Kiran: It is very clear that any power management and optimization technique applied at the gate level is too late to make any difference to the aggressive low power requirements. Early power planning, RTL power estimation, automated reduction around both registers and memories and early power intent verification is the only way to achieve today’s aggressive power goals for both mobile as well as wired chips. Stop by Atrenta’s booth (#2230) to talk about Kiran’s views with him! Note: Lee PR does work for Atrenta Tags: 49DAC, Atrenta, DAC 2012, Kiran Vittal, power management, power optimization, RTL |
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