As I recently shared, UVVM, VHDL’s long-awaited alternative to UVM, promises to be interesting. Later this week, I’ll be joined by Espen Tallaksen, Bitvis Managing Director and Founder for a joint webinar, UVVM – A game changer for FPGA VHDL Verification.
Below, please find Espen Tallaksen’s recent guest blog on the topic that originally appeared on the Aldec Blog.
FPGA VHDL Verification
How can we do this faster and with better quality – at no extra cost?
by Espen Tallaksen, Bitvis Managing Director and Founder
This is actually possible – and with an average efficiency improvement of 20 to 50% for medium to high complexity FPGAs. Less for data path oriented designs and more for control or protocol oriented designs. At no extra cost.
All that is required is that you do your testbench development the same way you do your design. Every single FPGA designer knows that a good top level design architecture is critical. Most FPGA designers also know that a good microarchitecture is at least as important for module design. It should thus be obvious that a good architecture is also equally important for your testbench, but for some strange reason most testbenches do not have the same good architecture as the design being verified.
Most designers agree that the following are critical for an efficient development of a high quality design module:
– Overview, Readability, Simplicity
– Modifiability, Maintainability, Extendibility
– Debuggability
– Reusability
So why should testbenches be any different, with on average the same time usage as the actual design?
The DVCon Europe conference is certainly growing, and the methodology presented yearly continues to be more mature and ready to use. This year’s DVCon Europe was not thematically different from other conferences. Subjects like 
