Posts Tagged ‘standards’
Wednesday, December 11th, 2013
 Here at the Aldec corporate office, we have a sign that reminds us all of our mission in the field of Technology. It reads, ‘To deliver solutions that provide the highest productivity to value ratio; supporting our existing products while delivering innovation to current and new technologies’. We have similar statements to reaffirm our commitment in the areas of Research, Alliances, and Culture – we call it our “Aldec DNA”.
 Because we genuinely want to have a clear understanding of our user’s requirements and methodology preferences, we continually engage in surveys and interviews. The knowledge we gain better positions us to support our existing products and to deliver that support where it matters the most to our users. If you’ve ever had that frustrating experience where your favorite tool no longer supports your methodology of choice – then you understand why this is so important.
Our Commitment to the VHDL Community
When it comes to VHDL-2008, we have learned from our customers that many are happy using the methodology – and continue to successfully deliver cutting-edge technology with it. So, while we remain committed to delivering innovation to new technologies, our R&D teams also invest a great deal of development time to ensure that Aldec solutions continue to offer a high level of support for popular languages like VHDL.
For the rest of this article, visit the Aldec Design and Verification Blog.
Tags: Active-HDL, advanced verification platform, Aldec, aldec design rule checker, aldec dna, aldec simulators, alint, bitvis, do-254/ed-80 vhdl rule plug-ins, eda industry, embedded psl, FPGA Design, functional coverage, HDL, highest productivity to value ratio, ieee, ieee 1076-1993 Standard, ieee 1076-2002 vhdl standard, ieee 1076-2008 standard, ieee standard, ieee vhdl, intelligent testbench methodology, open source vhdl verification methodology, osvvm, psl embedded in vhdl, randomization, Riviera-PRO, simulation, source encryption, standards, starc vhdl, vector implementation of integer arithmetic, verification, VHDL, vhdl community, vhdl designs, vhdl testbench, vhpi interfacing to C/C++ code
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Wednesday, August 28th, 2013
 As the proud Product Manager of Aldec’s FPGA Design Simulation solution, I am excited (like it was my first Cranberries concert) to announce that Active-HDL™ is celebrating 16 years since its initial release in 1997. Active-HDL has not merely stood the test of time, it has dominated the FPGA market like a Hulk Hogan smackdown with powerful simulation performance and debugging tools.
The key to Active-HDL’s long-term success lies in Aldec’s customer-centric philosophy. Simply put, we really do listen closely to our users and invest heavily in our tools. For this reason, continued simulation performance optimizations from release to release enable users to benefit from Active-HDL’s faster simulation even as the size of FPGA designs continues to grow.
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Tags: Active-HDL, Aldec, assertions, cen, chinese electronics news, co-simulation, coverage, debugging, debugging tools, design, digital, documentation, FPGA, fpga design simulation solution, fpga designs, HDL, ieee, matlab, os-vvm, project management, semiconductor industry, simulation, simulation platform, standards, top fpga design, university, verification, verification platform, verilog, VHDL, Xilinx
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Wednesday, June 26th, 2013
 An Interview with FAA Consultant DER, Randall Fulton
A few weeks ago I had the opportunity to sit down with an avionics industry certification expert, FAA Consultant Designated Engineering Representative (DER), Randall Fulton. We began discussing common mistakes in DO-254 projects, and then branched out to many different areas including future of DO-254, industry engineering best practices, and his advice to organizations new to DO-254.
Louie: In your experience, what are the common mistakes in DO-254 projects?
Randall: Starting certification liaison activities and the SOI-1 planning audit after the design already exists. Many projects also need to read the additional guidance from the FAA in Order 8110.105 to understand the impact and be prepared to show the data to satisfy the Order. Organizations also underestimate the resources required for a project. This includes staffing as well as managing all the data. Another common area is not appreciating the impact of effective requirements writing skills.
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Tags: Aldec, compliance, do-254, FPGA, fpga interface, pld vendors, safety-critical, SoC, standards, verification
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Here at the Aldec corporate office, we have a sign that reminds us all of our mission in the field of Technology. It reads, ‘To deliver solutions that provide the highest productivity to value ratio; supporting our existing products while delivering innovation to current and new technologies’. We have similar statements to reaffirm our commitment in the areas of Research, Alliances, and Culture – we call it our “Aldec DNA”.
Because we genuinely want to have a clear understanding of our user’s requirements and methodology preferences, we continually engage in surveys and interviews. The knowledge we gain better positions us to support our existing products and to deliver that support where it matters the most to our users. If you’ve ever had that frustrating experience where your favorite tool no longer supports your methodology of choice – then you understand why this is so important.
