EDACafe: Aldec Design and Verification

Aldec Design and Verification

Posts Tagged ‘hardware’

FPGA-Based Prototyping Q&A: 100 Million Gates and Beyond

Wednesday, July 30th, 2014

I am a Hardware Technical Support Manager. Ask Me Anything!

Earlier this summer, I joined a team traveling from Aldec’s R&D offices in Kraków, Poland to attend the annual Design Automation Conference (DAC) in San Francisco. As Technical Support Manager for Aldec’s Hardware Products Division, my goals for this event were two-fold. First, as we’ve made huge enhancements to our HES-7™ FPGA prototyping solution in the past year, I wanted to be there in person to share more about them in demos and presentations at the Aldec booth.

Secondly, and really my favorite part of DAC, I wanted to hear from engineers in the field looking for solutions to their real-world problems. Sometimes I have immediate answers for their questions, like the engineer who was not happy with their current solution’s implementation time or the fellow that needed support for in-house development boards. Occasionally though, I don’t have an immediate answer and instead they’ve given me valuable ideas that I get to take back home to my team so we can set to work developing solutions.

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Tags: Aldec, FPGA, fpga prototyping solution, fpga-based prototyping q&a, hardware, HES-7, prototyping, SoC and ASIC Prototyping
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SCE-MI for SoC Verification

Wednesday, September 18th, 2013

Today’s System-on-Chip verification teams are moving up in the levels of abstraction to increase the degree of coverage in the system design. As designs grow larger, we start to see an increase in test time within our HDL simulations. Engineers can utilize Hardware-Assisted approaches such as simulation acceleration, transaction-level co-emulation, and prototyping to combat the growing simulation times of an RTL simulator. In this article, we’ll dive much deeper into the transaction-level co-emulation methodology.