Connecting Emulated Design to External PCI Express Device

These days verification teams no longer question whether hardware assisted verification should be used in their projects. Rather, they ask at which stage they should start using it.

Contemporary System-on-Chip (SoC) designs are already sufficiently complex to make HDL simulation a bottleneck during verification, without even mentioning hardware-software co-verification or firmware and software testing. Thus, IC design emulation is an increasingly popular technique of verification with hardware-in-the-loop.

Recently, hardware assisted verification became much more affordable thanks to the availability of high capacity FPGAs (like Xilinx Virtex UltraScale US440) and their adoption for emulation by EDA vendors.

A good example of such an emulation platform is Aldec’s HES-DVM. It can accommodate designs over 300 Million ASIC gates on multi-FPGA boards (HES-US-1320), where the capacity scales by interconnecting multiple boards in a backplane.

Design compilation, synthesis and partitioning are fully automated by the DVM tool which is part of the HES-DVM platform. Worried about tracing design problems and debugging while in emulation? Not a problem. HES-DVM has a HW Debugger tool that can capture design signals across multiple FPGAs and correlate them with your RTL design hierarchy, so the waveforms captured from emulation look as if they had been captured during an HDL simulation.

There are other advantages to using emulation, one of which clearly differentiates this verification method from others. Emulation allows you to connect the emulated design with real devices known as In-Circuit-Emulation (ICE), and this is the subject I wish to elaborate on in this blog.

Connecting an emulator with an external environment is an advanced use case and usually requires some additional up-front effort, but it pays off in the long run because less effort is required to create complex test scenarios.

Now, live data streams will stimulate your design under test.

However, please be advised that all the great features of emulation – such as fully automatic design setup and sophisticated debugging capabilities – come at the price of slower than real-time design clocks.

A typical emulation clock frequency will be between 1 and 10MHz. It becomes obvious that in many cases such clocks are too slow to communicate with external peripherals directly. Thus, the ‘additional up-front effort’ mentioned above is with regards to the development of Speed Adapters, which buffer data and provide cross-domain crossing (CDC) between the slower emulation domain and the usually faster peripheral device domain. It’s also important that the Speed Adapters remain transparent for both domains.

For the rest of this article, visit the Aldec Design and Verification Blog

Tags: ARM, asic, embedded, Emulation, FPGA, HES-DVM, simulation, SoC, verification

Categories: Emulation/Acceleration, FPGA Design, FPGA Design Creation and Simulation, TySOM EDK

This entry was posted on Monday, May 4th, 2020 at 2:29 pm. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.