ARM-based SoC Co-Emulation using Zynq Boards

Have you ever worked on a group project where you had to combine your work with that of a colleague of a different engineering discipline but the absence of an efficient means of doing so affected the project’s overall outcome? Well, for software and hardware engineers developing an SoC, the merging of their respective engineering efforts for verification purposes is a big challenge.

Early access to hardware-software co-verification allows hardware and software teams to work concurrently and set the foundation to a successful SoC project. However, many co-emulation methodologies are based on processor virtual models which are not accurate representations of the design. Fortunately, Aldec has a solution that integrates an ARM-based SoC from Xilinx, specifically a Zynq UltraScale+ MPSoC, with the largest Xilinx UltraScale FPGA. Since the Zynq device includes the hard IP of the ARM processor, our solution provides an accurate representation of the ARM-based SoC design for co-verification.

Figure 1: Aldec’s HW/SW Co-Verification

Design specification is the first step of the design flow in which the required specifications of the product are defined. By defining the features, requirements, and functionalities, we set the foundation for the design.

 Next comes IP-based design and RTL coding, which consists of writing code for custom functional blocks in a hardware description language such as VHDL, Verilog or SystemVerilog. Along with the RTL code, testbenches are created to simulate and ensure functionality of the design according to its specifications. Riviera-PRO can be used to create testbenches and debug a design during simulation. Riviera-PRO is an advanced verification platform that provides high performance simulation and advanced debugging in VHDL, Verilog, SystemVerilog, SystemC, and mixed languages.

Software development starts in parallel with RTL coding. However, software and hardware developers seldom, if ever, communicate during this stage. The lack of communication between the two teams creates challenges such as not having an accurate hardware model for software development and debugging. Aldec’s solution enables early and accurate hardware and software co-verification using the ARM hardened core inside the TySOM-3-ZU7EV device, as shown in Figure 1, eliminating several ARM-based SoC verification challenges.

But what are the challenges?

Figure 2 shows the typical hardware and software components of SoCs. Challenges include not having access to the ARM pure RTL codes nor virtual platform, an accurate and fast hardware model for software development, low HDL simulation speed, and a limited number of tests with which to cover all the design functionality. As a design becomes larger and more complex, so simulation takes longer to run; sometimes up to a few months. Since it is not possible to develop a direct test to verify the whole functionality of an SoC design, we are faced with using a constrained random verification methodology, like UVM, to improve functional coverage. However, constrained random tests generate extremely long test sequences, which then becomes a bottleneck in the verification process. Moreover, the constrained random methodology doesn’t address the disconnected verification of hardware and software. The design would therefore benefit from co-emulation, which handles designs with a large number of gates without speed degradation; along with providing other benefits.

For the rest of this article, visit the Aldec Design and Verification Blog

Tags: ARM, asic, embedded, Emulation, FPGA, HES-DVM, SoC, SoC and ASIC Prototyping, Validation, verification, Zynq

Categories: Emulation/Acceleration, FPGA Design, FPGA Design Creation and Simulation, TySOM Boards, TySOM EDK

This entry was posted on Wednesday, February 19th, 2020 at 8:40 am. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.