Code Coverage in HDL Editor? Now That’s a Nice Feature.

For a long time I have been a fan of code coverage tools that are embedded into the simulators themselves, and which give you the ability to switch easily between the code and the coverage results. It is particularly helpful to have a way of navigating the hierarchy, selecting a coverage result and then being able to look into the source code and make changes.

I recently had occasion to explain to someone how the feature works in Aldec’s Riviera-PRO, and to reflect on the tool developments that led to this great capability. As you may be aware, Aldec has a number of legacy coverage tools that allow you to view the coverage results from within the simulator; and which give you easy access to the coverage results and the corresponding lines of code. With the introduction of our unified coverage database – in .acdb format – it became possible to see the code coverage results in a more flexible format. The biggest boost, in my opinion, was the introduction of a cross-probing capability.

For those of you who are wondering how to use this feature.

• Open Riviera-PRO 2016.06 or newer and run your design with Coverage Enabled.
• Open the datasets window (View-> Hierarchy and Objects-> Datasets).
• Right-click in the window and select Add.
• Add the .acdb file associated with your design (it should show up as Simulation n, where n is number).
• Click on the newly added database.

For the rest of this article, visit the Aldec Design and Verification Blog.

Tags: coverage, Riviera-PRO, verification, verilog, VHDL

Category: Functional Verification

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