Synthesis of Energy-Efficient FSMs Implemented in PLD Circuits

Well, summer has been and gone; and for most of us it was a time to relax and reflect on our working practices. What can we do to achieve better results? And what can we do to break out of the routine of working on so many revisions?

For me, one of my summer break ponderings was thinking back on a trick I learned while working with my colleagues at the Silesian University of Technology.

CMOS technology is the one that has dominated all applications of digital circuits. Power consumed by a CMOS digital circuit is the sum of two components: static power and dynamic power. The static power is a characteristic feature of the technology process used, and is associated with leakage currents in steady state. The dynamic power consumed by a CMOS gate is proportional to average switching activity at the output of the gate, which describes how often the state at the gate output is changing. The dynamic power component can thus be considered and minimized in the appropriate process of logic synthesis.

The essence of logic synthesis oriented toward energy-efficiency requires finding a circuit structure in which the number of state transitions is minimized.

Switching global clock networks are responsible for a significant part of the total power dissipated by a CMOS VLSI circuit. That’s why many engineers try to block the clock signal to achieve power reductions in synchronous circuits.

Programmable Logic Devices (PLDs), and especially Field Programmable Gate Arrays (FPGAs), constitute a relatively new and rapidly developing branch of digital electronics. Constantly growing logic capacities at moderate prices make PLDs an attractive platform for not only prototyping but also short- and medium-volume production.

It is not always obvious though how best to map logic structures (resources) within a given PLD architecture when designing with energy-efficiency in mind. In particular, implementing clock gating is difficult, as PLD circuits contain dedicated clock networks, which do not contain any gating elements. “Disabling” the clock signal in PLD structures can be accomplished in two ways: firstly, by utilizing the “Enable Clock” inputs of memory elements or, secondly, by distributing the clock signal using local clock lines or general-purpose routing resources (which enable the insertion of logic gates). For the rest of this article, visit the Aldec Design and Verification Blog.

Tags: FPGA, fsm, ICCMSE2017, Low-power, Riviera-PRO, university, verification

Category: FPGA Design

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