Aldec Design and Verification 
Krzysztof Szczur
Krzysztof joined Aldec in 2001 and was a key member of the team that developed HES-DVM™, Aldec's FPGA-based simulation acceleration and emulation technology. He has worked in the fields of HDL IP-core verification, testbench automation and design verification for DO-254 compliance gaining … More » Acceleration-Ready UVM Webinar with Doulos and AldecApril 6th, 2016 by Krzysztof Szczur
Doulos CTO, John Aynsley, and I will be presenting a free 1 hour training webinar, Acceleration-Ready UVM, on Wednesday April 13th, 2016. Learn more in this guest blog by John Aynsley, excerpted from the Aldec Design and Verification Blog. Acceleration-Ready UVM by Doulos CTO, John Aynsley We hear that emulation is one of the fastest-growing segments in EDA right now, yet simulation still continues to be the main workhorse for functional verification, and SystemVerilog and UVM are everywhere you look. But how do you combine the two? How do you run a UVM-based constrained random verification environment alongside an emulator and get reasonable execution speed? Many vendors have solutions, including Aldec with their HES-DVM™ emulator. Their solution is based on the Accellera SCE-MI standard, and in particular on SV-Connect, which is a function-based interface that uses the SystemVerilog DPI (Direct Programming Interface) to pass information between the host and the emulator. You partition your UVM drivers and monitors into two parts, a small proxy that remains on the host and a synthesizable implementation that goes into the emulator. That way, all of the low-level timing detail is removed from the UVM code running on the host and is placed in the emulator, where it belongs. The communication between the host and the emulator can be optimized to avoid the emulator being stalled while waiting for the slower UVM simulation running on the host.
You can start investigating the UVM coding style needed to run alongside an emulator right now by taking advantage of Doulos’ Easier UVM Code Generator running on EDA Playground. We provide a specific example that demonstrates the use of split transactors, which you can run live over the web. You can find out more by attending a free webinar, Acceleration-Ready UVM, which will run in multiple time zones on Wednesday 13th April 2016. Click here to register. Tags: acceleration, Emulation, hardware, systemverilog, uvm, verification Categories: Emulation/Acceleration, Functional Verification |
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