‘UVM Really is Everywhere’ at DVCon Europe

According to the official email newsletter sent out in advance of DVCon Europe 2015 in Munich, top of the list of topics for the tutorial day is “Basic UVM, advanced UVM, UVM reuse, all things UVM”. This makes me smile, because UVM continues to be one of the hot training topics for us at Doulos. UVM really is everywhere, and that’s a good thing because, to cut a long story short, the UVM standard is catalyzing the adoption of coverage-driven verification across a broad community of engineers.

But that’s not the end of the story. SystemVerilog is an enormously large and complicated language. UVM is a large and complicated class library. Back in 2011, recognizing the difficulty that many users would face getting to grips with UVM, Doulos first introduced Easier UVM in an attempt to make UVM more accessible to a wider audience. Easier UVM started out as a way of thinking about and learning UVM that would make UVM approachable by ordinary VHDL and Verilog users as well as by verification experts. Since that time, Easier UVM has evolved to become a comprehensive set of UVM coding guidelines and a UVM code generator, which are open and freely available on the web. You can get Easier UVM from www.doulos.com/easier.

It seems the folks at Aldec agree with us that many users will need a helping hand with UVM because they have leveraged the Easier UVM Coding Guidelines in their approach to hardware-assisted acceleration running on their HES-DVM™ emulator. By adapting the code from the Easier UVM Code Generator, Aldec has been able to demonstrate a test environment that is acceleration ready, through the use of the Accellera SCE-MI standard.

Tags: FPGA Co-emulation, Hardware-Assisted Verification, uvm, UVM Hardware Assisted Acceleration

Category: Functional Verification

This entry was posted on Wednesday, November 4th, 2015 at 4:19 pm. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.