Aldec Design and Verification 
Sunil Sahoo
Sunil is Corporate Applications Engineer at Aldec. Sunil provides support for customers exploring simulation tools as an Aldec Applications Engineer. His practical engineering experience includes areas in, Digital Designing, Functional Verification and Wireless Communications. He has worked in wide … More » ‘Don’t Be Afraid of UVM’ Webinar on YouTubeOctober 27th, 2015 by Sunil Sahoo
Designers are usually very busy doing their work and have little time left for experimentation with new methodologies. Unfortunately for them, official documentation of UVM (Universal Verification Methodology) was written by Verification Engineers for Verification Engineers, concentrating on high-level features and completely neglecting lower-level details such as connecting UVM testbench to your design. Our webinar starts with solid review of SystemVerilog interfaces with special attention paid to Virtual Interfaces. Then it proceeds to Sequences and other Data Items, processed by Sequencers and fed to the design under test via Drivers. The role of Monitors and Scoreboards in analysis of results is explained. The presentation concludes with environment configuration and running test from the top-level module. For the rest of this article, visit the Aldec Design and Verification Blog. Tags: design, hardware, resources, systemverilog, uvm, verification, Webinar, YouTube Category: Functional Verification |
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