Helping FPGA Designers get started with UVM

Here is a excerpt from John Ansley’s recent guest blog:

UVM (the Universal Verification Methodology for SystemVerilog) represents best practice in constrained random functional verification, so it is something that every digital design and verification engineer should be aware of.

However, even if you already have a sound understanding of SystemVerilog, UVM is in itself complex and challenging to learn and use; a daunting prospect, particularly if you are an FPGA designer with limited time to dedicate to verification.

The challenge of getting your first UVM project off the ground

Even assuming the highest quality training, there is still a need for further help to get started with the first project. UVM can take some time to adopt – in some areas there is more than one approach to choose from, there are optional shortcuts and new features that may or may not work for you and finding good quality advice can be hard and time-consuming in the absence of a definitive methodology. Many have observed that UVM is still in need of a “methodology”, in the sense of a definitive set of rules and guidelines directing its use.

Making the path to UVM adoption Easier

Since the introduction of UVM in 2011, Doulos has been developing Easier™ UVM to act as a starting point for learning UVM and it has now evolved into a comprehensive set of coding guidelines with an open-source UVM code generation….

Tags: design, FPGA, Functional Verification, Riviera-PRO, uvm

Category: FPGA Design

This entry was posted on Tuesday, September 8th, 2015 at 4:29 pm. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.