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 Aldec Design and Verification

Archive for September, 2015

Helping FPGA Designers get started with UVM

Tuesday, September 8th, 2015
Doulos has partnered with Aldec to deliver this Friday’s webinar, ‘Easier UVM: Helping FPGA Designers Get Started with UVM’ . Presented by Doulos CTO, John Aynsley, the 1 hour webinar includes live Q&A so it’s a great opportunity to find out how Easier UVM can work for you. The webinar includes examples from the Easier UVM Code Generator running under Aldec Riviera-PRO™.

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