Louie De LunaLouie is responsible for FPGA level in-target testing technology and requirements lifecycle management for DO-254 and other safety-critical industry standards. He received his B.S. in Computer Engineering from University of Nevada in 2001. His practical engineering experience includes areas in Acceleration, Emulation, Co-Verification and Prototyping, and he has held a wide range of engineering positions that include FPGA Design Engineer, Applications Engineer, Product Manager and Project Manager.
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Louie De LunaLouie is responsible for FPGA level in-target testing technology and requirements lifecycle management for DO-254 and other safety-critical industry standards. He received his B.S. in Computer Engineering from University of Nevada in 2001. His practical engineering experience includes areas in
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For DO-254 Compliance, Hardware Flies Not Simulations
February 20th, 2014 by Louie De Luna
DO-254 defines 3 types of verification methods: Analysis, Test and Review. In order to satisfy the verification objectives defined in DO-254, applicants must formulate a requirements-based verification plan that employs a combination of the three methods.
Analysis vs. Test
A computerized simulation of the hardware item is considered an Analysis. Test is a method that confirms the actual hardware item correctly responds to a series of stimuli. Any inability to verify specific requirements by Test on the device itself must be justified and alternative means of verification must be provided. In DO-254, the hardware test is far more important than the simulation. Certification authorities favor verification by test for official verification credits because of the simple fact that hardware flies, not simulation models. Requirements describing pin-level behavior of the device must be verified by hardware test.
Defining the Problem
Testing the FPGA device at the board level provides very low FPGA input control making it difficult to inject certain signals for normal range and robustness tests. Frequently as a result, applicants are left with the option to verify the requirements only by simulation. But simulation is insufficient and in many cases unable to expose errors that may impact safety and reliability of the device under test. Verification of requirements by hardware test during final board testing is challenging and not feasible in most cases.
For the rest of this article, visit the Aldec Design and Verification Blog.
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Tags: Aldec, capture requirements, develop test cases, develop testbench, device testing with do-254/cts, do-254, final board testing, FPGA, fpga device, functional simulation code coverage, increase verification coverage by test, simulation, simulation models, test vectors for device testing, timing simulation, verification, verification methods
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