Aldec Design and Verification 
Jerry Kaczynski
Jerry serves as Aldec’s Research Engineers and possesses over 20 years of experience in HDL language & tool training, technical writing, application and research engineering. He is an IEEE and Accellera committee member, involved in the development of industry standards for VHDL, Verilog, … More » Why Randomize?September 24th, 2013 by Jerry Kaczynski
After presenting a conference paper on how to do OSVVM-style constrained random and intelligent coverage (randomization based on functional coverage holes), I received a great question, “Why Randomize?” The easiest way to answer this is with an example. Let’s look at a FIFO test – test a FIFO, write to it, read from it, write to it and read from it simultaneously, fill it and see that additional writes are held off successfully, and empty it and see that additional reads are held off successfully. Most certainly a FIFO can be tested using a directed test (just code, no randomization). The following simulation waveform shows diffcount (the number of words in the FIFO) for a directed test. The lowest value is empty. The highest is full. Using this, you can visually check off all of the required conditions and see that the FIFO is indeed tested. For the rest of this article, visit the Aldec Design and Verification Blog. Tags: Aldec, coverage, fifo test, functional coverage holes, intelligent coverage, os-vvm, osvvm-style constrained random, randomization, systemverilog, VHDL, vhdl testbench techniques Category: Functional Verification |
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