SCE-MI for SoC Verification

Today’s System-on-Chip verification teams are moving up in the levels of abstraction to increase the degree of coverage in the system design. As designs grow larger, we start to see an increase in test time within our HDL simulations. Engineers can utilize Hardware-Assisted approaches such as simulation acceleration, transaction-level co-emulation, and prototyping to combat the growing simulation times of an RTL simulator. In this article, we’ll dive much deeper into the transaction-level co-emulation methodology.

Co-Emulation is a transaction-level oriented Hardware-Assisted verification method, as opposed to event-based using simulation acceleration. Hardware and software communicate via messages, which can translate to hundreds of clock cycles in hardware, and conversely, hundreds of clocks cycles in HW can translate to a single message in software. The Standard for Co-Emulation Modeling Interface (SCE-MI) was developed by Accelera so that SoC designs can run at their full performance potential in hardware emulation platforms. This is done with a set of synthesizable transactions, which are bus functional models which translate high level messages to signal level interfaces.

For the rest of this article, visit the Aldec Design and Verification Blog.

Tags: accelera, Aldec, co-simulation, dpi, Emulation, FPGA, function-based, hardware, hardware emulation platform, hardware-assisted verification method, hardware-assisted verification solution, hdl simulations, high-level testbenches, macro-based, pipes-based, prototyping, rtl simulator, sce-mi, simulation acceleration, SoC, SoC and ASIC Prototyping, soc designs, standard for co-emulation modeling interface, system-on-chip verification, systemverilog direct programming interface, systemverilog lrm, transaction-level co-emulation, transaction-level co-emulation methodology, Validation, verification

Categories: Emulation/Acceleration, SoC Design and Validation

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