Posts Tagged ‘UVM registers’
Monday, May 20th, 2019
Being so immersed in the work and technology, it’s easy to forget where we are in this technological revolution. Some of us didn’t really appreciate the impact of the internet until we held it in our hands and swiped to the next pages of seemingly infinite information. In the last decade, we saw how the automotive industry converted most of their mechanical systems into electronics and added Advanced Driving Assistance Systems (ADAS) for the safety of the passengers and other vehicles. We saw how home automation has transformed our daily life with the help of Automatic Speech Recognition (ASR) and low-power wireless technology.
The next decade ahead is even more exciting as new generation of SoCs will power new artificial intelligence (AI) applications that will touch human lives and transform various industries across the board. For sure, the associated design and verification challenges and cost will only increase, and that’s why the EDA community has been preparing for it with the help of standards from Accellera such as UVM and now PSS.
As a company focused on design/verification of critical aspects of SoCs, we understand our place and know our role. Our goal is two-fold: automate verification and minimize functional flaws. At this year’s Design Automation Conference (DAC) in Las Vegas NV, we will showcase our most innovative solution yet that is built on top of our core code-generation technology. We call it Specta-AV™ – a massive UVM testbench generator that automates verification and minimizes functional flaws that originate from errors or changes in the spec.
UVM has been good and useful to us, and will continue to do so in the coming decade. But UVM is notorious for two main problems: its steep learning curve and the staggering amount of UVM code required to verify a full SoC. Verifying a custom IP with one master and slave agent requires tens of thousands of lines of UVM code. Verifying a full SoC requires multi-million lines of UVM code (in addition to the array of standard VIPs). Automating the process of creating UVM code is critical, and is a great solution to these two problems.
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Tags: Agnisys, Design and Verification, Embedded, Free register Generator, UVM, UVM registers
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Sunday, March 31st, 2019
As generations of designs evolved from a few hundred transistors to hundreds of billions, our industry abstracted the problem space from transistors to schematics to gates, and from RTL bit-level to transaction-level. Using abstraction, designers were able to focus on the high-level design and tests while the tools took care of the automation and calculations at the low-level – this certainly made the design flow more efficient and engineers more productive. Over the years abstraction has allowed the EDA industry to manage the ever-increasing complexity and scale of ASIC/SoC designs.
On a related note, check out Mark Glasser’s blog regarding his perspective on abstraction(while your there check out his great photography too).
The strategy behind the Portable Test and Stimulus Standard (PSS) is again to raise this level of abstraction to the next level. PSS will enable SoC teams specify stimulus and tests at a high-level. PSS has constructs for modeling high-level test scenarios such as data flow (buffer, streams, states), behavior (actions, activities, components, resource, pooling), constraints, randomization and coverage. The PSS tool generates the downstream code reusable from block, subsystem and system-level, which can be re-targeted for various verification platforms such as simulation, emulation, prototyping or post-silicon validation.
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Tags: Agnisys, Assertions, Automation, functional verification, IDesignSpec, ISequenceSpec, ISS, PSS, UVM registers, Verification
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Thursday, January 24th, 2019
Tools are made to automate a process, perform calculations, minimize errors and improve efficiencies, but at their core, tools are made to solve a given problem. Problems are found as a natural effect of progress. They come from the industry – in some cases from experts, innovators and tool vendors, and often times they come directly from the users or customers. As an EDA tool vendor, we serve highly-intelligent users who know their design and verification problems well as these have become roadblocks in their day to day work. But honestly these problems will not reach the tool vendor if there’s no mutual trust to begin with. I’m not referring to the routine support tickets that are filed, but to the technical problems that openly come up during face-to-face discussions. That’s our case with our portable sequence generator.
A few longtime users of our register generator tool shared with us their need to centralize the creation of sequences. The basic idea is to reuse the successful concept that we have in centralizing the creation of registers from a single spec – this concept has unified the IP, software, firmware, device driver and system integrator teams to work from a single source. Any changes to the register spec would typically only involve re-generation of the RTL, UVM regmodel, UVM testbench, C/C++ headers and documentation from the spec itself using built-in code generators. You don’t have to worry about which design and verification elements are impacted due to the register change, and you don’t have to manually modify a long list of register files to implement the change. Many of our users have found this concept and methodology valuable, so they have asked us to do the same thing for sequences.
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Tags: Design and Verification, ISequenceSpec, Register Generator, Specification, UVM, UVM registers, Verification
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