It’s hard to think of any electronic design automation (EDA) innovation that’s had more impact than the Universal Verification Methodology (UVM). After decades of ad hoc designer-centric simulation and a few advanced verification teams using more automated methods, the UVM brought everyone involved in chip development into a new era. Verification engineers have ready access to object-oriented programming, constrained-random stimulus, self-checking tests, reusable models, functional coverage, assertions, and more. Both the UVM itself and the SystemVerilog language upon which it is built are industry standards, allowing teams to mix EDA tools from multiple vendors, and easily switch tools if they wish.

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