Posts Tagged ‘ISequenceSpec’
Sunday, March 31st, 2019
As generations of designs evolved from a few hundred transistors to hundreds of billions, our industry abstracted the problem space from transistors to schematics to gates, and from RTL bit-level to transaction-level. Using abstraction, designers were able to focus on the high-level design and tests while the tools took care of the automation and calculations at the low-level – this certainly made the design flow more efficient and engineers more productive. Over the years abstraction has allowed the EDA industry to manage the ever-increasing complexity and scale of ASIC/SoC designs.
On a related note, check out Mark Glasser’s blog regarding his perspective on abstraction(while your there check out his great photography too).
The strategy behind the Portable Test and Stimulus Standard (PSS) is again to raise this level of abstraction to the next level. PSS will enable SoC teams specify stimulus and tests at a high-level. PSS has constructs for modeling high-level test scenarios such as data flow (buffer, streams, states), behavior (actions, activities, components, resource, pooling), constraints, randomization and coverage. The PSS tool generates the downstream code reusable from block, subsystem and system-level, which can be re-targeted for various verification platforms such as simulation, emulation, prototyping or post-silicon validation.
(more…)
Tags: Agnisys, Assertions, Automation, functional verification, hsi, IDesignSpec, ISequenceSpec, ISS, PSS, UVM registers, Verification
No Comments »
Thursday, January 24th, 2019
Tools are made to automate a process, perform calculations, minimize errors and improve efficiencies, but at their core, tools are made to solve a given problem. Problems are found as a natural effect of progress. They come from the industry – in some cases from experts, innovators and tool vendors, and often times they come directly from the users or customers. As an EDA tool vendor, we serve highly-intelligent users who know their design and verification problems well as these have become roadblocks in their day to day work. But honestly these problems will not reach the tool vendor if there’s no mutual trust to begin with. I’m not referring to the routine support tickets that are filed, but to the technical problems that openly come up during face-to-face discussions. That’s our case with our portable sequence generator.
A few longtime users of our register generator tool shared with us their need to centralize the creation of sequences. The basic idea is to reuse the successful concept that we have in centralizing the creation of registers from a single spec – this concept has unified the IP, software, firmware, device driver and system integrator teams to work from a single source. Any changes to the register spec would typically only involve re-generation of the RTL, UVM regmodel, UVM testbench, C/C++ headers and documentation from the spec itself using built-in code generators. You don’t have to worry about which design and verification elements are impacted due to the register change, and you don’t have to manually modify a long list of register files to implement the change. Many of our users have found this concept and methodology valuable, so they have asked us to do the same thing for sequences.
(more…)
Tags: Design and Verification, ISequenceSpec, Register Generator, Specification, UVM, UVM registers, Verification
No Comments »
Friday, April 27th, 2018
 Verification and Validation are two sides of the same coin
In 2011, Intel discovered a design flaw in its Sandy Bridge combination graphics-microprocessor chip that led to not only a major production delay but that ultimately cost more than $1 billion in replacement costs and lost revenue. If you’re searching for a clear-cut example as to why finding bugs early in the development process is always a top priority, look no farther than that. A product recall can be a terrible experience for everyone involved, but the costs associated with that recall alone are the stuff that nightmares are made of.
Yet at the same time, the complexity of the modern SoC environment has made things difficult in this regard to say the least. Getting SoC to market (and doing so with quality) is such an enormous task that teams are always looking for newer and more innovative ways to shorten the development time. The situation has also raised the requirement to incorporate verification and validation as a one-step process to catch bugs from an early design stage. Bringing the enormous tasks of verification and validation closer together is great news for the entire semiconductor industry.
This, however, is where the concept of “shift left” enters the conversation. As its name suggests, “shift left” is a series of activities and processes that better position design teams to anticipate and address downstream issues upfront, thus fixing a small problem now before it becomes a much bigger (and more expensive one) tomorrow. It’s the heart of the idea that you should “test early and often.” It also does so in a way that has proven to shorten development times so that no time is wasted late in the process where every second counts.
Why This Matters
But before we can focus on the importance of “shift left,” we must first address the early stages of this process in general. Verification and Validation are two critical steps in the creation of electronic systems, but over the last few years, in particular, their roles (and how those roles relate to one another) has changed.
In the modern era, there is an urgent need to enable users to describe the programming and test sequences of a device in a way that automatically generates sequences ready to use from an early design and verification stage, all the way up through post-silicon validation.
Tags: ISequenceSpec, SemiEDA, Verification
No Comments »
|
