Archive for the ‘Uncategorized’ Category
Tuesday, March 3rd, 2020
The consumer revolution over the past few decades has funneled a growth of SoC chips primarily in the area of consumer electronics. This revolution along with the increase of automotive and industrial electronics has led to a trend in convergence of applications on a single device. Companies vying for a bigger share of the market place are enticing their consumers by offering new or better features, which often adds to design complexities. In this competitive food chain, chip design companies are tragetting the companies developing these consumer devices with a range of functionalities embedded in single chip solutions. This convergence in applications as well as the growth of new technologies such as IoT, augmented reality, AI etc. has resulted in increasing demands on design complexity and design performance. With an increase in design complexity and a reduction in time to market, chip designers are now grappling with ways to meet the performance requirements while at the same time reduce the design cycle.
Consequently, design teams are increasingly compelled to look at methodology changes that can help accelerate chip assembly through one or multiple forms of automation.
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Tags: Agnisys, Design Assembly
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Friday, February 21st, 2020
The complex SoCs of today typically contain thousands of registers, which are used to control the operations of the SoC/IP. The register specification, which is at the epicenter of a SoC/IP design is accessed by different teams such as hardware, software, verification and embedded design teams, all of which need to access the same source. A mismatch and misinterpretation of the specification simply results in un-necessary delays to the development cycle.
While there are several methods to define the register specification, such as Excel, Word, IP-XACT etc., SystemRDL is gaining popularity, as it is an easy-to-use textual language used for the design and delivery of SoCs/IPs. Released by Accellera, SystemRDL supports the complete project cycle of registers from the specification, model generation, and design verification to maintenance and documentation. It mitigates the problems encountered in describing and managing registers. SystemRDL enables a system architect or a hardware designer to create a functional specification of the hardware-software interface (HSI) for an SoC/IP, which can include addressable registers, interrupts, counters etc. This specification is then used by other members of the team including software, hardware and design verification to create representations of data in the languages they use in their aspect of the SoC development process.
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Wednesday, September 11th, 2019
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Agnisys invites you to join our Live Webinar:
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Presented by: Nikita Gulliya, Agnisys R&D Engineer
IDesignSpec has become the de-facto solution for register design/verification. It has helped in the industry minimize SoC functional flaws that show up due to changes and errors in the functional specification by employing a golden specification methodology.
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Register for a time that is convenient for you.
Thursday, September 19, 2019
3:00PM – 4:00PM CEST
Thursday, September 19, 2019
11:00AM – 12:00PM PDT
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IDesignSpec offers a wide-range of features and capabilities for various design use cases and strategies. As requested by many of our users, in this webinar, we will show you several design strategies and tips/tricks used by power-users of IDesignSpec.
We will cover:
- Tool Overview
- Tips and Tricks
- Building a Hierarchical Specification
- Customizing the generated RTL
- Widely-used RTL Properties
- Parameterization
- Connecting custom RTL to the auto-generated register block
- Creating a TCL as a top-level check for limiting access types, register types, field widths
- Feature-based availability at block, register and field level
- Q & A
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Tags: IDesignSpec, Register Design, webinar
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Tuesday, February 19th, 2019
By Louie De Luna, Agnisys Director of Sales and Marketing
Right after Google’s AlphaGo system defeated a human Go world champion in 2015, the hype of deep learning and machine learning (ML) was quickly assimilated into mainstream technology. In EDA, the application of ML algorithms actually dates back to 2008 – when two Machine Learning-related topics were presented at DAC. The first topic, Efficient System Design Space Exploration Using Machine Learning Techniques targeted design challenges and the second, Experiences and Advances in Formal and Dynamic Verification, targeted verification challenges.
As a company focused on solving both design and verification challenges associated to Hardware/Software Interface (HSI), Agnisys has extensive experience in register code generation and verification, so applying Machine Learning to register automation is a natural next step for us. Agnisys register tool IDesignSpec is a fully-matured solution with a large user base, where it can generate register code directly from the specification in Word, Excel, IP-XACT or SystemRDL. But in an ideal world, our users would rather use plain and simple English text to describe the register behavior rather than use special properties and syntax. Natural, plain English is still the hallmark of specifications in today’s system design and a lot of useful and actionable information is embedded in the natural language specification text.
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Tags: Agnisys, Automation, DVCon, Free register Generator, functional verification, hsi, IDesignSpec, Register Generator
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