Setting a High Standard for Standards-Based IP

In a post last year, I discussed our recently announced Standard Library of IP Generators (SLIP-G™). This library has proven to be quite popular with our users, and that’s not surprising. Reuse plays a big role in system-on-chip (SoC) development since no team can afford to design and verify a billion or more gates from scratch. There’s no chance of this trend reversing, so we see a lot of interest in many types of design and verification IP, especially those that implement industry standards. We’ve been hard at work supporting users and expanding our IP titles, so I’d like to revisit the topic in this post.

It’s important to stress that we offer a library of IP generators, not fixed IP blocks. This is essential given the diversity of applications that use SoCs as well as the mix of technologies (FPGA, ASIC, and full custom) used to build these complex chips. Every chip project has its own requirements for its IP blocks, with a selection of features often arising from tradeoffs between speed, area, and power. Only a generation-driven solution can satisfy these needs. Options and customization must be built into the generators so that users are never tempted to manually edit register-transfer-level (RTL) design files.

SLIP-G generates the IP RTL code, which is integrated with the user’s portions of the design into the full SoC. Our SoC Enterprise™ (SoC-E) automates this process and works seamlessly with SLIP-G. However, we provide much more than the design. For every IP, SLIP-G also generates Universal Verification Methodology (UVM) models to help build the verification testbench and a set of programming sequences to initialize and configure the registers of the selected block. In addition, we generate C/C++ sequence application programming interfaces (APIs) for use in developing firmware and drivers that access the IP block.

Finally, we generate documentation professional enough to be delivered to the end users of the SoC. SLIP-G helps every group involved in SoC development: hardware designers, verification team, lab bring-up/validation engineers, and technical writers. We even provide output files that can be used when developing automated test equipment (ATE) programs for production chips in the manufacturing process. We set a high standard for delivering standards-based IP and, as we expand our library, we are continuing to offer the same quality and flexibility for all new titles.

SLIP-G launched last year with four IP blocks: General Purpose Input/Output (GPIO), I2C, Timer, and Programmable Interrupt Controller (PIC). These have many configuration and customization options to meet the requirements across a diverse user base, and I gave examples in my previous post. So far this year, we have introduced four more entries in our library: Direct Memory Access (DMA), Serial Peripheral Interface (SPI), Pulse Width Modulation (PWM), and Advanced Encryption Standard (AES). These are numerous options available when generating these blocks with SLIP-G.

DMA allows SoC subsystems to access main system memory independent of the central processing unit (CPU). This frees up the CPU for important computational work rather than simply moving data around. Our DMA IP has two masters and four channels, with built-in round-robin arbitration across the channels. It can handle transfers from memory to peripheral, peripheral to memory, peripheral to peripheral, and memory to memory. It offers a configurable number of channels and includes an interrupt controller for status and diagnostics.

SPI is a synchronous serial interface specification used for short distance communication. The CPU uses the SPI registers to program our IP block to initiate a transaction. The data length, command length, and address length are all configurable. Options include whether interrupts are generated with an enable or a mask. PWM is a way to control analog devices with a digital output by modulating an output signal. It is one of the primary means by which processors drive analog devices such as variable-speed motors, dimmable lights, actuators, and speakers. Our PWM IP block features:

• Customizable number of PWM output signals
• Customizable number of external sources
• A prescaler register to generate the PWM signals on a slower clock than the system clock
• Customizable widths for control registers
• Standard APIs to program the block

AES is a standard used to encrypt and decrypt sensitive electronic data, applicable to both hardware and software. It can handle three different key sizes (128, 192 and 256 bits) and supports a 128-bit block size. We support 128-bit keys and 128-bit blocks. During IP generation the user can choose whether the key value is provided to the block via an input signal or defined in the RTL code. If the latter, then the user specifies the key value. Other customization options include whether the block is configured for encryption or decryption.

SLIP-G also allows user customization such as adding fields to existing registers, adding additional registers, adding logic to the IP, and setting up dependencies on events within the IP block. We continue to add new generation options based on user requests, and we continue to grow the library. We recently joined the Mobile Industry Processor Interface (MIPI) Alliance and are considering developing MIPI-based IP. Their standards span camera, displays, power management, and more, so we expect that there will be significant interest in our user base.

Please let us know if you have any suggestions for new IP titles or new features for existing blocks. We’re proud of our SLIP-G family and its unique support for hardware reuse, verification reuse, programming sequence reuse, and documentation reuse. As I said in my previous post, we’re pleased to be able to help you create ever bigger SoCs without exploding your team sizes or project schedules. The more types of standards-based IP we can offer, the more powerful this statement is.

Anupam Bakshi

Tags: RTL, SemiEDA

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