In a post last year, I discussed our recently announced Standard Library of IP Generators (SLIP-G™). This library has proven to be quite popular with our users, and that’s not surprising. Reuse plays a big role in system-on-chip (SoC) development since no team can afford to design and verify a billion or more gates from scratch. There’s no chance of this trend reversing, so we see a lot of interest in many types of design and verification IP, especially those that implement industry standards. We’ve been hard at work supporting users and expanding our IP titles, so I’d like to revisit the topic in this post.
It’s important to stress that we offer a library of IP generators, not fixed IP blocks. This is essential given the diversity of applications that use SoCs as well as the mix of technologies (FPGA, ASIC, and full custom) used to build these complex chips. Every chip project has its own requirements for its IP blocks, with a selection of features often arising from tradeoffs between speed, area, and power. Only a generation-driven solution can satisfy these needs. Options and customization must be built into the generators so that users are never tempted to manually edit register-transfer-level (RTL) design files.
