Over the last couple of months, I have discussed some key recent additions to the Agnisys solutions for system-on-chip (SoC) automation, including three new products announced at this year’s virtual Design Automation Conference (DAC). These innovations continue our history of building upon our expertise in the automation of register design and verification to encompass many other aspects of embedded systems development. We provide real value to your architects, designers, verification engineers, software developers, technical writers, and chip testers.
The key idea that links all our products and solutions is using an executable specification as the single source of information across all your project teams. From a single specification, you can generate design RTL, complex programming and test sequences, UVM testbench models for simulation, portable stimulus standard (PSS) models, assertions for formal verification, C code for firmware and device driver development, CSV files for automatic test equipment (ATE), and end-user documentation in multiple formats.
No duplication of information means no wasted time, money, or resources and no chance for multiple representations to get out of sync as the project evolves. Changes to the specification require only the push of a button to update all generated files. We support a wide range of specification formats, including industry standards such as IP-XACT and SystemRDL, popular tools such as Microsoft Word and Excel, and our own specialized editors. We generate output files in dozens of different formats to support the diverse users in your teams.
