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 Agnisys Automation Review

Archive for May, 2019

Not your Average UVM Testbench Generator – Unveiling at DAC 2019

Monday, May 20th, 2019

Being so immersed in the work and technology, it’s easy to forget where we are in this technological revolution. Some of us didn’t really appreciate the impact of the internet until we held it in our hands and swiped to the next pages of seemingly infinite information. In the last decade, we saw how the automotive industry converted most of their mechanical systems into electronics and added Advanced Driving Assistance Systems (ADAS) for the safety of the passengers and other vehicles. We saw how home automation has transformed our daily life with the help of Automatic Speech Recognition (ASR) and low-power wireless technology.

The next decade ahead is even more exciting as new generation of SoCs will power new artificial intelligence (AI) applications that will touch human lives and transform various industries across the board.  For sure, the associated design and verification challenges and cost will only increase, and that’s why the EDA community has been preparing for it with the help of standards from Accellera such as UVM and now PSS.

As a company focused on design/verification of critical aspects of SoCs, we understand our place and know our role. Our goal is two-fold: automate verification and minimize functional flaws. At this year’s Design Automation Conference (DAC) in Las Vegas NV, we will showcase our most innovative solution yet that is built on top of our core code-generation technology. We call it Specta-AV™ – a massive UVM testbench generator that automates verification and minimizes functional flaws that originate from errors or changes in the spec.

UVM has been good and useful to us, and will continue to do so in the coming decade. But UVM is notorious for two main problems: its steep learning curve and the staggering amount of UVM code required to verify a full SoC. Verifying a custom IP with one master and slave agent requires tens of thousands of lines of UVM code. Verifying a full SoC requires multi-million lines of UVM code (in addition to the array of standard VIPs). Automating the process of creating UVM code is critical, and is a great solution to these two problems.


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