It may be summertime, but the folks in the Verification world are clearly not taking any holidays.
This week, four different verification-related news announcements arrived, presenting an interesting set of positive mid-year perspectives: Breker’s new round of funding, EVE and Synopsys’ co-emulation success, Cadence’s beefed-up PCIe VIP, and a new co-simulation interface from Aldec and Agilent. Good news on all fronts and now these folks should take a vacation!
The concept of a Grand Challenge is an established one in engineering, so here in 2012 what are the Grand Challenges in EDA? Let’s go out on a limb and name a few candidates:
No.1) Low power: This is the critical problem here in the era of mobile everything. If you can’t guarantee low power for your device, it’s going to go dark way too soon and be way too hot in the meanwhile. Great challenges remain in perfecting the tools to make this all happen.
No.2) Formal verification: There just has to be a way to guarantee that what we meant to design, has been designed and then manufactured. Isn’t that the goal of formal verification, and isn’t it true that we’re not quite there yet?
No.3) 3D-ICs: In the last several years, this one’s gotten a lot of attention, but it appears that there’s still a lot of work to do – at least on the logic side of the equation. Clearly more tools are needed.
It’s stranger than fiction, but there are actually two different entities at DAC that bear the name BDA, and they’re both acronyms.
One is a company very familiar to the EDA space, Berkeley Design Automation. As you know, President & CEO Ravi Subramanian has just been elected to a second term as a member of the Board of Directors of EDAC.
Subramanian’s BDA is in the news again this week because they just announced that ATopTech, also an EDA company, is now using BDA’s Analog FastSpice to “enhance the accuracy of the timing analysis in [ATopTech’s] Aprisa P&R product for designs at advanced process technology nodes such as 28nm and 20nm..”
So what is the other BDA at DAC? It’s Biological Design Automation. The International Workshop on Biological Design Automation figured large on Sunday and Monday, June 3rd and 4th, in San Francisco where it was again co-located with the Design Automation Conference, as it has been for several years.
Article source: Cosmic Circuits
Cosmic Circuits, a leading provider of differentiated Analog, Mixed-Signal and Connectivity IP cores, today announced the silicon availability of its MIPI M-PHY solution in 28nm.
Cosmic Circuits offers a broad portfolio of differentiated Analog IP cores in nanometer technology nodes covering Data-Converters, Analog-Front-End platforms for Wireless and Audio, Power-Management, Clocking and MIPI Interfaces.
Cosmic Circuits M-PHY solution supports both the HS-G1 (1.5Gbps) and HS-G2 (3Gbps) modes and is available in multiple process technologies ranging from 85nm to 28nm. The silicon has been characterized across supply, temperature and process corners and detailed characterization reports will be available very soon. Here is a video showcasing Cosmic Circuits validation platform and methodology for the MIPI M-PHY:
