|Clock Domain Crossing (CDC) Design Techniques || In today’s era of complex SoCs various design sub-blocks running at different
frequency are common occurrence. Even with today’s advance functional verification solutions, CDC signals pose unique and challenging issues. While STA is an integral part of the timing closure solutions, it does not address the issue of proper CDC implementation. To say the least, CDC issues if not detected in late design stages or worst during post-silicon validation can lead to heavy financial penalties.
Various issues caused by CDC can be bracketed into two basic problems,
1. Issue of meta-stability propagation.
2. Functional issues due to signal crossing clock domains.
The following article describes design methods to avoid the above two problems.
|FPGA Floorplanning || Floorplanning is the process of identifying structures that should be placed close together, and allocating space for them in such a manner as to meet the sometimes conflicting goals of available space (cost of the chip), required performance, and the desire to have everything close to everything else.
|A Technical Tutorial on Digital Signal Synthesis|| Direct digital synthesis (DDS) is a technique for using digital data processing blocks as a means to generate a frequency- and phase-tunable output signal referenced to a fixed-frequency
precision clock source. In essence, the reference clock frequency is “divided down” in a DDS architecture by the scaling factor set forth in a programmable binary tuning word. The tuning word is typically 24-48 bits long which enables a DDS implementation to provide superior output frequency tuning resolution.
|A tutorial on incremental design using FPGAs from Actel|| An "incremental" design flow is highly desirable with regard to repairing or optimizing parts of the design without disturbing portions that have met their design requirements.
|Accelerating 4K/2K&3D DCP creation for Cinema Encoding|| The PRISTINE accelerates JPEG 2000 encoding up to 113 2K frames per second. It also supports a wide range of resolutions up to 4K. Embedded intoPIX technology provides the ultimate in pristine picture quality and meets the DCI recommendations.
|Actel Quick Start Guide|| The Actel Quick Start Guide for Libero IDE contains information for using the Libero IDE software to create designs for, and program, Actel devices. This manual includes information about the Libero IDE software, which allows you to generate
and/or import a netlist generated from a third-party CAE tool, perform pre-synthesis simulation, synthesize your design, place-and-route the design, run physical synthesis, perform static timing
analysis, extract timing information, estimate power consumption, and generate a programming file to program an Actel FPGA.
|Actel Quick Start Guide for Libero IDE v8.0|| The Actel Quick Start Guide for Libero IDE contains information for using the Libero IDE software
to create designs for, and program, Actel devices.
This manual includes information about the Libero IDE software, which allows you to generate
and/or import a netlist generated from a third-party CAE tool, perform pre-synthesis simulation,
synthesize your design, place-and-route the design, run physical synthesis, perform static timing
analysis, extract timing information, estimate power consumption, and generate a programming file
to program an Actel FPGA.
This manual also refers to other Actel documents that contain additional information, including
CAE software interface guides and simulation guides with specific information about using CAE
tools with the Libero IDE.
|ADC Architectures III: Sigma-Delta ADC Basics|| The sigma-delta (Ó-Ä) ADC is the converter of choice for modern voiceband, audio, and high-resolution precision industrial measurement applications. The highly digital architecture is ideally suited for modern fine-line CMOS processes, thereby allowing easy addition of digital functionality without significantly increasing the cost. Because of its widespread use, it is important to understand the fundamental principles behind this converter architecture.
|Advancing FPGA design flows using Chronology's TimingDesigner|| This tutorial explores a technique for determining necessary clock skew for balanced read data capture margins with DDR memory interface designs.
|AMBA TestBencher Pro|| AMBA demonstrates how to create and use an AMBA AHB master. It makes extensive use of Pipeline Boundary Markers in the master transactors which are used to model the pipeline behavior defined by the AMBA specification. "Blocking Samples" in the master write and read transactions are used to wait for HREADY. Loop Markers in the master idle and busy transactors insert variable number of idle or busy cycles. State Variables and "Store Sampled Value As Subroutine Output" variables in the master write transactor are used to pass the read data back to the sequencer process. There is also a User-defined Class Method that determines the burst length based on a given burst code (defined by AMBA spec.). And finally the project makes use of Constrained randomization so that idle and busy transactors are applied using a random number of idle or busy cycles.
|An introduction to Floorplanning Xilinx FPGAs|| Floorplanning is the process of identifying structures that should be placed close together, and allocating space for them in such a manner as to meet the sometimes conflicting goals of available space (cost of the chip), required performance, and the desire to have everything close to everything else.
Within the Xilinx chips it is often the case that the smallest area design is also the highest performance design. This flies in the face of many design methodologies, where area and speed are considered to be things that should be traded off against each other.
|APS X84 FPGA VHDL Synthesis Lab Book|| A NO NONSENSE guide and tutorial designed to get you from concept through VHDL coding, synthesis, routing and into the hardware quickly !
|Are VMEbus & VME64X Really Compatible?|| VMEbus, a bus that has been
around since Pac-Man, remains a
dominant embedded architecture.
The creation of VME64X
breathed in new life, and soon,
VITA 41 and 46 will further
extend this legacy. What happens
when you want to upgrade your
legacy VMEbus system? Can you
add a higher performing
VME64X board or must you
scrap the system and start over
with VME64X? If you build a
VME64X system, can you insert
VMEbus cards into it?
|ARM programming Tutorial||
|ARM® Cortex™-M1 Embedded Processor Hardware Development Tutorial|| This document shows you how to create a Cortex™-M1 processor system that runs on one of the Actel Fusion
embedded development kit boards. This design can be used as a starting point for developing your Cortex-M1
embedded system targeting Actel’s Fusion FPGA devices.
|ARM®Cortex™-M1 Embedded Processor Software Development Tutorial|| This tutorial shows you how use the Actel tools to develop a software application for a Cortex™-M1–based embedded
processor system. After completing this tutorial you will be familiar with the software design process which includes the
• Creating the SoftConsole project
• Configuring the SoftConsole complier/linker settings
• Compiling your code
|Automated video algorithm implementation|| This article presents an overview of a C-based design flow that enables designers to generate high-quality hardware for video algorithms. Algorithmic C synthesis is used to generate optimized RTL from algorithmic specification written in pure ANSI C++. A wide range of micro-architectures for ASIC and FPGA target technologies can be generated from the same source by interactively setting directives during synthesis
|Backplane Wiring Know How|| Question: How are power bugs, lugs, taps, screw studs, and power nuts related? Answer: All are backplane jargon for power terminals. Most engineers don’t need to know these terms because they purchase enclosures that have the backplane and power supply integrated at the factory. There is little concern about how they are wired. However, if you need to replace a backplane or power supply, or if you install a backplane and wire the power supply into a custom enclosure, these terms suddenly become important.
|Basic Ciruit Analysis|| From time to time, questions arise on various forums about how to calculate the dropping value of a resistor, or design a voltage divider. You'd be amazed at how simple these things are if you understand three basic laws.
|Basic DAC Architectures I: String DACs and Thermometer (Fully Decoded) DACs|| Rather than simply treating DACs as black boxes having a digital input and an analog output, it is much more useful to understand the fundamental DAC architectures in use today. This can also aid in the selection process which can be somewhat daunting considering the sheer number of DACs currently on the market.
This tutorial examines the most fundamental DAC architectures, the "string" DAC and the "thermometer" DAC. String DACs had their origin with Lord Kelvin, who invented the Kelvin divider in the mid-1800s. String DACs are popular today, especially in applications such as digital potentiometers where resolutions of 6 to 8 bits are typical. Because of their relative freedom from code-dependent switching glitches, thermometer DACs are popular building blocks in low distortion segmented DACs as well as in pipelined ADCs.
|Basic electrical laws & circuits theory|| Direct currents circuits
Alternating currents circuits
|Boolean Algebraic Expressions|| Although not as convenient as in some SPICE implementations, it is possible to implement Boolean algebraic expressions in B2 Spice as part of the non-linear voltage or current source or otherwise. Some methods of doing this are presented here.
|Boundary Scan Tutorial|| In this tutorial, you will learn the basic elements of boundary-scan architecture where it came from, what problem it solves, and the implications on the design of an integrated-circuit device.
|Cadence Encounter Flow Management System (FMS)|| For any medium to large chip, design management is just as important as the design itself. Keeping the flow and files organized is a must if you have tough timing challenges and need to keep a number different runs for comparison. And once you have a a dozen or so flow scripts, how do you manage them? How can you easily reuse them in the next project? And shouldn't there be scripts that came with Encounter that we could leverage?
|Cadence Encounter Tutorial|| Cadence Encounter goes far beyond Silicon Ensemble. It offers a single cockpit for the entire physical implementation flow. Although some tools are run as external binaries (e.g. Nanoroute), the user never has to leave the GUI. In addition, the Common Timing Engine is integrated into Encounter, allowing for timing analysis every step of the way.
|Cadence Interoperability using OpenAccess 2.0|| OpenAccess is a central storage database for the next generation EDA design flow. It replaces GDS and DEF, as well as many other text files. The entire design flow moves from a file based system to a database system.
OpenAccess is developed by Si2 in collaboration with all major EDA vendors.
|Cadence Virtuoso and Encounter Interoperability using OpenAccess 2.2|| This tutorial illustrates the flow between Cadence Encounter and Cadence Virtuoso using OpenAccess 2.2. The biggest change in OA22 is the integration of logical netlist data into the database. While OA20 made GDS and DEF obsolete, now Verilog gate level netlists are obsolete as well. OA22 uses the Embedded Module Hierarchy (EMH) to store the netlist data. To import an external gate level netlist, use "verilog2oa".
|Compact PCI Voltage (I/O) and VMEbus/Compact PCI Connectors: Keeping 'Em Straight|| Have you ever turned on your
CompactPCI chassis for the
first time to find some boards
didn’t power up? It is not uncommon
to discover that the
cause is a missing Voltage (I/
O) jumper. Not only is this
very irritating, it’s compounded
by a lack of documentation.
Many times, the CompactPCI
enclosure is shipped with the V
(I/O) jumper and keys uninstalled
leaving you responsible
for properly configuring the V
(I/O). The following provides
background on V(I/O) you
should know to solve your dilemma.
|Comparator design using verilog|| Verilog is one of the commonly used hardware description language. Comparator is used to compare the inputs and has three ouputs to denote the condition greater than (A>B), less than (A verilog program
|Conformal Logic Equivalence Checking (LEC)|| This tutorial provides a quick getting-strated guide to Cadence Conformal logic equivalence checking. The basic flow is to input both an RTL netlist and a synthesized netlist and then have Conformal check whether both netlists are equal. Think of it as an LVS for Verilog. This is a powerful tool to get a formal proof that the output from Synthesis matches the original RTL code without having to run simulation
|Converting Oscillator Phase Noise to Time Jitter|| A low aperture jitter specification of an ADC is critical to achieving high levels of signal-to-noise ratios (SNR). (See References 1, 2, and 3). ADCs are available with aperture jitter specifications as low as 60-fs rms (AD9445 14-bits @ 125 MSPS and AD9446 16-bits @ 100 MSPS). Extremely low jitter sampling clocks must therefore be utilized so that the ADC performance is not degraded, because the total jitter is the root-sum-square of the internal converter aperture jitter and the external sampling clock jitter. However, oscillators used for sampling clock generation are more often specified in terms of phase noise rather than time jitter. The purpose of this discussion is to develop a simple method for converting oscillator phase noise into time jitter.
|Core-assisted approach accelerates debug of FPGA DDR II interfaces|| In this "How To" tutorial, a debug methodology is described and applied to a real FPGA-based DDR II high-speed memory controller debug example.
|Core8051s Embedded Processor Hardware Development Tutorial|| This tutorial shows how to develop a simple 8051-based embedded processor system using Actel design tools. This design is suitable as a starting point for developing an embedded system. It is assumed that the reader is familiar with the FPGA design flow using Actel tools. Actel provides tutorials for both Libero® Integrated Design Environment (IDE) and SmartDesign on the Actel website in addition to training classes.
|Core8051s Embedded Processor Software Development Tutorial|| This tutorial shows how to develop a simple application program for an 8051-based embedded processor system using Actel tools. This design is suitable as a starting point for developing an embedded system. It is assumed that the reader is familiar with the C programming language. After completing this tutorial you will be familiar with the software design process for creating an 8051-based embedded system using SoftConsole.
|Creating a pure::variants Model from a CSV File|| This tutorial shows the use of the pure::variants Synchronization Framework for creating
and synchronizing pure::variants models from external data sources. The tutorial example
is the import and update of feature models from CSV1 files.
The synchronization framework is used by several pure::variants extensions like the Synchronizer
for Doors and the Synchronizer for CaliberRM as well as the Connector for
Source Code Management.
|Creating Analog Testbenches for Fusion Designs|| This tutorial demonstrates how to create analog testbenches for Fusion FPGAs using Libero® IDE
and WaveFormer Lite.™This tutorial assumes basic knowledge and experience with the Libero IDE design flow and
WaveFormer Lite testbench generation tool.
|Custom Daughter Card Design for NI Single-Board RIO with NI Multisim and Ultiboard|| NI Single-Board RIO products are low-cost embedded deployment solutions based on NI CompactRIO. They integrate a real-time processor, reconfigurable field-programmable gate array (FPGA), and analog and digital I/O on a single board and are powered by NI LabVIEW Real-Time and LabVIEW FPGA technologies. The built-in analog and digital I/O can be expanded using C Series modules.
|DC UPS Or how to keep your networking gear going 24/7|| Typical networking devices use "Black Block" type wall adapters to drop the main voltage to 9V-18V or higher. A wall transformer presents a large inductive load for inverters and is not recommended for use with computer UPS systems.
|Design and Operation of Automatic Gain Control Loops for Receivers in Modern Communication Systems|| This article is intended to provide insight into the effective operation of variable gain amplifiers (VGA) in automatic gain control (AGC) applications. Figure 1 is a general block diagram for an AGC loop. The input signal passes through the VGA to produce the output level to be stabilized.
|Digital Electronics|| Digital Electronics
|Digital System Tutorial|| In science, technology, business, and, in fact, most other fields of endeavour, we are constantly dealing with quantities. Quantities are measured, monitored, recorded, manipulated arithmetically, observed, or in some other way utilized in most physical systems. It is important when dealing with various quantities that we be able to represent their values efficiently and accurately. There are basically two ways of representing the numerical value of quantities: analog and digital.
|Direct currents devices|| Electronic component are classed into either being Passive devices or Active devices. A Passive Device is one that contributes no power gain to a circuit or system. Examples are Resistors, Light Bulb, Electrical Heaters. Active Devices are components that are capable of generating voltages or currents. Examples are Batteries and other Electrical Curent & Voltage Sources.
|DOWNLOAD MOZAIX TUTORIALS|| The Mozaix tutorials are designed to run with Mozaix version 3.0. Some tutorials require specific designs, which must be downloaded in order to run the tutorial successfully.
|DOWNLOAD PANTHEON TUTORIALS|| Each Pantheon tutorial takes approximately 60-90 minutes to complete. To open a tutorial, click below on a PDF icon located to the left of the tutorial title. If the tutorial runs with an Intercept demo design, click on the link located in the 'Design Name' column. Download the correct demo based on the selected tutorial and your operating system.
|Dynamic Power Analysis|| Encounter stores the transient power consumption an a database. The suggested viewer is "nWave", which ships with Encounter 4.1.
|EDA & Tools|| About the EDA Industry: EDA stands for Electronic Design Automation. To understand the rapidly growing, three and one-half billion dollar EDA industry, it helps to define what we mean for the words behind those three letters, "EDA".
|EDA Tutorial|| This is a rough guide to what EDAs are and how they work, with some information specific to my project. The only technical requirements for viewing this are a standards-compliant web browser and a Macromedia Flash viewer for some of the animated illustrations.
|EE 4743/6743 Digital System Design (Spring 2003)|| This is an upper level course, and thus is taught in a different style than what I use in a lower level course. READ THIS -- it will give you a clue as to what to expect in this class.
|EE 8993 VHDL Modeling Course (Spring 2004)|| In terms of course prerequisites, I am assuming that everybody is already familiar with RTL-level VHDL via the Digital System Design course (ECE 4743/6743) or some other source. This object of this course is to introduce the student to more of the VHDL modeling language than what has been covered in previous courses. We will also cover aspects of Verilog which do not overlap VHDL functionality, and look at mixed-mode simulation.
|Exporting trace data|| Tutorial on Exporting trace data
|FPGA design tutorial|| This FPGA design tutorial covers various issues in the fields of FPGA design, simulation and synthesis. It is targeted towards both beginners and experienced FPGA designers.
|FPGAs for Software Radio|| In the last decade, ASICs (application
specific ICs) and DSPs have been deployed
to handle nearly all the signal
processing functions associated with radio
communications. Even though field-programmable
gate arrays have been around for
decades, the latest generation of FPGAs is so
powerful that it is now displacing both
ASICs and DSPs in the latest software radio
applications. Furthermore, a new class of
design tools opens up FPGAs to both hardware
and software engineers. Debugging
these new devices has been greatly simplified
by excellent modeling and analysis tools.
Perhaps the most exciting new twist in
design tools is the growing libraries of IP
(intellectual property) cores available from
FPGA vendors, and a whole new industry
of third party companies that offer IP cores
for specific application areas.
|FPGAs Tackle DSP Applications for Communications|| For years, FPGA technology has been
a major cornerstone of board level
product design for embedded software
radio and communication systems.
FPGAs are ideal for implementing the data
formatting, timing, and the specialized glue
logic needed to connect real-time peripherals
like modems, A/D converters and digital
receivers to programmable processors.
However, with their newly acquired DSP
capabilities, FPGAs are now expanding
these traditional roles to help offload
computationally-intensive digital signal
processing functions from the processor.
|General and Specialized Feature Design Tutorials|| There are several tutorials shipped with all versions SynaptiCAD's software. These tutorials demonstrate
everything from how to draw basic timing diagrams to advanced VHDL and Verilog simulation
techniques. The following chart describes the recommended tutorials for each of our
|Generating a Xilinx FPGA Netlist from C-Language|| This Getting Started tutorial demonstrates how to compile C code into HDL, and then synthesize the HDL using Xilinx ISE. This tutorial assumes that you already know the basics of C-to-HDL compilation.
|Generating an Altera FPGA Netlist from C-Language|| This Getting Started tutorial demonstrates how to compile C code into HDL, and then synthesize the HDL using Altera Quartus II. This tutorial assumes that you already know the basics of C-to-HDL compilation.
|Generating C/C++ style flags|| This tutorial shows how to generate C/C++ style flags with pure::variants. The flags are
modeled in a family model and setup a transformation generating the defines for the selected
|Generating HDL from C-Language|| This Getting Started tutorial demonstrates how to compile a simple digital signal processing (DSP) filter written in C into HDL, ready for FPGA synthesis. The goal of this application will be to generate a 16-bit, 12-tap FIR filter as hardware in the form of either VHDL or Verilog. Although this is a relatively simple example in terms of the required lines of C code, it does illustrate some key concepts of Impulse C including the use of streaming and pipelining for high performance.
|Generating Makefiles|| This tutorial shows how to generate variable makefiles. For it the files will be added which
are needed for the build as well as compiler options set.
For the tutorial a configurable program will be create which prints a given number or the
square of the given number. A feature Square controls this behaviour. Additional it can be
able to select between Debug and Release build. For the Debug build it can be able to enable
|Generating Visual Studio Project Files|| This tutorial shows how to generate variable Visual Studio project files. As well as setting
project options, files which are needed for the build will be added.
For the purposes of the tutorial a configurable program will be creates that prints a given
number or the square of the given number. A feature, Square, controls this behaviour. Debug
and Release features may also be selected for the build.
|Guidelines for Chip Design For Test (DFT)|| In this 4-part document, we will look at DFT guidelines specific to the design of boards to be tested through the
boundary-scan registers of IEEE 1149.1-compliant devices. Since the 1149.1 structures are incorporated inside
the compliant devices, many of the guidelines relate to the specification of optional features inside the devices
i.e. are device-level DFT guidelines. Accordingly, the first part of the document considers the device-level
|Identify® RTL Debugger|| This simple tutorial teaches you how to instrument and debug a small HDL
design. The design is a simple 4-bit counter with a clock and reset. Two
versions of the counter are provided: one in VHDL and one in Verilog.This tutorial simulates hardware debug data by applying
randomly generated data to all instrumented nodes. This data
does not reflect the actual operation of the design and only serves
to show the format of the debug data.
|Implementing a Direct Stream Digital Decoder on National Instruments FPGA Platforms|| Super Audio CD® (SACD) is a high-resolution CD audio format developed by Sony and Philips. SACD uses Direct Stream Digital® (DSD) technology to oversample audio signals and store them as delta-sigma modulated digital audio. The sampling rate of DSD is 2.82 MHz, which is 64 times the CD audio sampling rate of 44.1 kHz. Because of the high sampling rate, DSD signals can represent analog signals more accurately than a regular CD can.
|Implementing a Fixed-Point Octave Filter on an FPGA Target|| Octave analysis is one of the most useful methods for analyzing sound and vibration systems. National Instruments provides the CompactRIO platform and LabVIEW FPGA technology that you can use to perform octave analysis. This document demonstrates how you can use the LabVIEW Digital Filter Design Toolkit to implement a fixed-point octave filter on an FPGA target.
|Improving Design Productivity with Multisim, LabVIEW and PXI|| One of the great hurdles in the modern design flow is the inability to effectively prototype a design and compare its behavioral measurements to the initial design specifications. This barrier to effective design is detrimental to engineers who want to be able to quickly verify and validate their prototypes with simulated behavior.
|Infrared detector arrays for thermal imaging (Tutorial "Infrared Detectors")|| Infrared detectors and detector arrays are used in many fields of applications today, both civilian and defence oriented. Many of these are based on passive detection of thermally emitted electromagnetic radiation as described by the wellknown Planck's law. In this way it is possible to image objects in darkness, or carry out contactless temperature measurement. Active systems, on the other hand, are basedon illumination of the object by an infrared source, such as a thermal emitter or an infrared laser.
|intoPIX JPEG 2000|| “JPEG 2000 is a new image coding system that uses state-of-the-art compression techniques based on wavelet technology. Its architecture should lend itself to a wide range of uses from portable digital cameras through to advanced pre-press, medical imaging and other key sectors.”
|Introduction to Timing Analysis|| Use real examples to analyze:
Reg 2 Reg Paths
Reg 2 Reg Paths with Clock Skew
|Kirchhoff's Current and Voltage Laws & circuit analysis|| KCL states that the algebraic sum of the currents in all the branches which converge in a common node is equal to zero
|LabVIEW Embedded Module for ADI Blackfin Processors - Evaluation Options|| The Analog Devices EZ-KIT evaluation boards provide a cost effective method for initial evaluation of the LabVIEW Embedded Module for Blackfin Processors. With these kits you can learn more about developing with ADI's processors and LabVIEW software tools.
|LabVIEW Real-Time 8.6 for CompactRIO Video Tutorials|| The LabVIEW Real-Time Module 8.6 introduces powerful new features for programming CompactRIO hardware that reduce development time and complexity as well as provide tools for monitoring and maintaining CompactRIO applications. These tutorial videos walk through each of the new features for CompactRIO.
|Life Science Applications of SPICE Simulation in NI Multisim|| Electronic designs play a vital role in the life sciences industry, especially in the biomedical and medical devices fields. From developing sensor devices acquiring milli-volt range signals in very sensitive environments, to signal conditioning circuitry, such as filters, amplifiers, and level shifters, and finally sending these signals to the digital domain including ADC design, engineers need to be equipped with best-in-class simulation and layout tools to be successful with their designs.
NI Multisim enables engineers in these domains to optimize their electronic circuits and rapidly create PCB prototypes with a high level of accuracy. Multisim also supports the development of other complementary circuits required for the design completion, such as display circuits, power supplies, custom connector boards and many others.
|Logic analyzers vs. Oscilloscopes|| Tutorial on Logic analyzers vs. Oscilloscopes
|Logical Expressions - B2 Spice v5 Gates|| Harvey Morehouse is a contractor/consultant with many years of experience using circuit analysis programs. His primary activities are in Reliability, Safety, Testability and Circuit Analysis. He may be reached at firstname.lastname@example.org. Simple questions for which I know the answer are free. Complex questions, especially where I am ignorant of the answers, are costly!!! Please confine your questions to the content of the articles.
|Logical Expressions - Ideal Diode, Perfect Diode, Ideal Zener Diode|| In the previous article of this series I showed how to create logical expressions using the uramp function. I alluded to their use in ideal/perfect perfect diode models, without going into details. I have had several inquiries from persons who could not see how to do this. To preclude more emails and have me typing much of the same information several times, I have decided to prepare an implementation of an ideal diode and a perfect diode, and describe how an ideal zener (or breakdown) diode could be created. This paper shows how to do these things.
|Logical Expressions - OTA1|| Harvey Morehouse is a contractor/consultant with many years of experience using circuit analysis programs. His primary activities are in Reliability, Safety, Testability and Circuit Analysis. He may be reached at email@example.com. Simple questions for which I know the answer are free. Complex questions, especially where I am ignorant of the answers, are costly!!!
|Lossless Compression of Image or Video for Archiving|| The PRISTINE radically accelerates JPEG 2000 encoding and decoding while supporting a wide range of resolutions up to 4K+ (4096x3112). Embedded intoPIX technology allows both Mathematically and Visually Lossless compression providing best-in-class pristine picture quality.
|Magnetics (Part 1) - Transformer Modeling|| This paper describes perfect and ideal transformers and provides the building blocks for constructing realistic models for simulations with multi-turn transformers and non-ideal inductors. This is not a magnetics primer, and assumes a basic knowledge of magnetics, especially in the parts to follow. The focus is on how to create models of real, lossy transformers of increasing complexity using an ideal transformer as a building block, and also non-ideal inductors.
|Magnetics (Part 2) – Creating more complex transformer models|| Part 1 described the perfect and ideal transformer models. This article, Part 2, shows how to create more complex ideal transformer realizations using the ideal transformer primitive. Also discussed are how to add parasitic and other non-ideal elements, including real core elements which provide core loss, magnetization and hysteresis to this model. Part 3 will discuss how to create a lossy inductor model with hysteresis.
|Magnetics (Part 3) – The Core Model|| Part 1 and Part 2 described the perfect and ideal transformer models, and how to add lossy elements to transformer models created with ideal transformer primitives. This part discusses the methods that can be used to create core elements which can include core loss, magnetization and hysteresis in these models.
|Magnetics (Part 4) - Core/transformer conversation|| Part 3 described a method of modeling a core. In another article, hopefully to be posted before this one, is a means of creating a simple, lossless, nonlinear core model. This article is intended to discuss some core considerations and misconceptions regarding cores. It does not pretend to be exhaustive or even rigorous, but nonetheless to illustrate some important points in a discussion format. I am, of course, playing the 'expert' while my friend, the questioner, is speaking in italics.
|Model 2501 105 MHz A/D, Real-Time Signal Processor & Recorder RTS Development Platform|| The Pentek RTS 2501 is a highly-scalable
real-time platform for acquiring, down-converting,
processing, analyzing and recording
radar signals. Integrating recently-introduced
A/D converters, digital downconverters,
FPGAs and signal processors, this system
allows the design engineer to take advantage
of the latest technology for signal processing.
Scalable from 1 to 80 channels in a single
6U VMEbus chassis, RTS 2501 serves equally
well as a development platform for advanced
research projects and proof-of-concept prototypes,
or as a cost-effective strategy for
deploying high-performance, multichannel
|MT-002: What the Nyquist Criterion Means to Your Sampled Data System Design|| A quick reading of Harry Nyquist's classic Bell System Technical Journal article of 1924 (Reference 1) does not reveal the true significance of the criterion which bears his name. Nyquist was working on the transmission of telegraph signals over a channel that was bandwidth limited. A thorough understanding of the modern interpretation of Nyquist's criterion is mandatory when dealing with sampled data systems. This tutorial explains in easy to understand terms how the Nyquist criterion applies to baseband sampling , undersampling, and oversampling applications.
|MT-003: Understand SINAD, ENOB, SNR, THD, THD + N, and SFDR so You Don't Get Lost in the Noise Floor|| Six popular specifications for quantifying ADC dynamic performance are SINAD (signal-to-noise-and-distortion ratio), ENOB (effective number of bits), SNR (signal-to-noise ratio), THD (total harmonic distortion), THD + N (total harmonic distortion plus noise), and SFDR (spurious free dynamic range). Although most ADC manufacturers have adopted the same definitions for these specifications, some exceptions still exist. Because of their importance in comparing ADCs, it is important not only to understand exactly what is being specified, but the relationships between the specifications.
|MT-004: The Good, the Bad, and the Ugly Aspects of ADC Input Noise– Is No Noise Good Noise?|| All analog-to-digital converters (ADCs) have a certain amount of "input-referred noise"— modeled as a noise source connected in series with the input of a noise-free ADC. Input-referred noise is not to be confused with quantization noise which only occurs when an ADC is processing an ac signal. In most cases, less input noise is better, however there are some instances where input noise can actually be helpful in achieving higher resolution.
|MT-005: Noise Power Ratio (NPR) – A 65-Year Old Telephone System Specification Finds New Life in Modern Wireless Applications|| The concept of Noise Power Ratio (NPR) has been around since the early days of frequency division multiplexed (FDM) telephone systems. The NPR is simply a measure of the "quietness" of an unused channel in a multi-channel system when there is random activity on the others. Noise and intermodulation distortion products fall into the unused channel causing less than ideal performance. Originally used to check 4-kHz wide voice channels in FDM links, the same concept is useful today in characterizing multichannel wideband communication systems – but there are some important differences in the modern measurement techniques.
|MT-006: ADC Noise Figure – An Often Misunderstood and Misinterpreted Specification|| Noise figure (NF) is a popular specification among RF system designers. It is used to characterize the noise of RF amplifiers, mixers, etc., and widely used as a tool in radio receiver design. Many excellent textbooks on communications and receiver design treat noise figure extensively (see Reference 1, for example)—it is the purpose of this discussion to focus on how the specification applies to data converters.
|MT-007: Aperture Time, Aperture Jitter, Aperture Delay Time – Removing the Confusion|| Perhaps the most misunderstood and misused ADC and sample-and-hold (or track-and-hold) specifications are those that include the word aperture. A simple model is shown in Figure 1, and the most essential dynamic property of a SHA is its ability to disconnect quickly the hold capacitor from the input buffer amplifier. Historically, the short (but non-zero) interval required for this action is called aperture time (or sampling aperture), ta. The actual value of the voltage that is held at the end of this interval is a function of both the input signal slew rate and the errors introduced by the switching operation itself.
|MT-009: Data Converter Codes—Can You Decode Them?|| Analog-to-digital converters (ADCs) translate analog quantities, which are characteristic of most phenomena in the "real world," to digital language, used in information processing, computing, data transmission, and control systems. Digital-to-analog converters (DACs) are used in transforming transmitted or stored data, or the results of digital processing, back to "real-world" variables for control, information display, or further analog processing.
|MT-010: The Importance of Data Converter Static Specifications – Don't Lose Sight of the Basics!|| In the 1950s and 1960s, dc performance specifications such as integral nonlinearity, differential nonlinearity, monotonicity, no missing codes, gain error, offset error, and drift, etc., were primarily used to characterize data converters. These specifications were adequate during this era, because most early applications (with the exception of PCM and radar, for example) dealt with dc or low frequency signals such as those encountered in industrial measurement and process control. With the advent of microprocessors and digital signal processing (DSP) in the 1970s and 1980s, dynamic performance specifications, such as signal-to-noise ratio (SNR),
|MT-011: Find Those Elusive ADC Sparkle Codes and Metastable States|| A major concern in the design of digital communications systems is the bit error rate (BER). The effect of the ADC noise on system BER can be analyzed, provided the noise is Gaussian. Unfortunately, ADCs may have non-Gaussian error codes which contribute to the BER in ways that are not predictable by simple analysis. Bit error rate may also be a concern in such instrumentation applications as digital oscilloscopes, especially when operating in the "single-shot" mode or when trying to capture infrequent transient pulses. An error code can be misinterpreted as a transient pulse, thereby giving a false result.
|MT-012: Intermodulation Distortion Considerations for ADCs|| Intermodulation distortion (IMD) is a popular measure of the linearity of amplifiers, gain blocks, mixers, and other RF components. The second and third-order intercept points (IP2 and IP3) are figures of merit for these specifications and allow distortion products to be computed for various signal amplitudes. RF engineers are quite familiar with these specifications, but confusion can arise when applying them to ADCs.
|MT-013: Evaluating High Speed DAC Performance|| Unlike an ADC which requires an FFT processor to evaluate spectral purity, a DAC produces an analog output which can be examined directly using a traditional analog spectrum analyzer. A challenge in DAC evaluation is generating the digital input that can range from a single-tone sinewave to a complex wideband CDMA signal. Direct digital synthesis techniques can be used to generate digital sinewaves, but more sophisticated and expensive word generators are needed to produce the more complex digitial signals.
|MT-015: Basic DAC Architectures II: Binary DACs|| While the string DAC and thermometer DAC architectures are by far the simplest, they are certainly not the most efficient when high resolutions are required. Binary-weighted DACs utilize one switch per bit and were first developed in the 1920s (see References 1, 2, and 3). Since then, the architecture has remained popular and forms the backbone for modern precision as well as high-speed DACs.
|MT-016: Basic DAC Architectures III: Segmented DACs|| When we are required to design a DAC with a specific performance, it may well be that no single architecture is ideal. In such cases, two or more DACs may be combined in a single higher resolution DAC to give the required performance. These DACs may be of the same type or of different types and need not each have the same resolution.
|MT-017: Oversampling Interpolating DACs|| Oversampling and digital filtering eases the requirements on the antialiasing filter which precedes an ADC. The concept of oversampling and interpolation can be used in a similar manner with a reconstruction DAC. For instance, oversampling is common in digital audio CD players, where the basic update rate of the data from the CD is 44.1 kSPS. Early CD players used traditional binary DACs and inserted "zeros" into the parallel data, thereby increasing the effective update rate to 4-times, 8-times, or 16-times the fundamental throughput rate.
|MT-018: Intentionally Nonlinear DACs|| Usually, we have emphasized the importance of maintaining good differential and integral linearity in data converters. However, there are situations where ADCs and DACs which have been made intentionally nonlinear (but maintaining good differential linearity) are useful, especially when processing signals having a wide dynamic range.
|MT-019: DAC Interface Fundamentals|| This tutorial outlines some important issues regarding DAC interface circuitry including the voltage reference, analog output, data input, and clock driver. Because ADCs require references and clocks also, most of the concepts presented in this tutorial regarding these subjects apply equally to ADCs.
|MT-020: ADC Architectures I: The Flash Converter|| Commercial flash converters appeared in instruments and modules of the 1960s and 1970s and quickly migrated to integrated circuits during the 1980s. The monolithic 8-bit flash ADC became an industry standard in digital video applications of the 1980s. Today, the flash converter is primarily used as a building block within subranging "pipeline" ADCs. The lower power, lower cost pipeline architecture is capable of 8- to 10-bits of resolution at sampling rates of several hundred MHz.
|MT-021: ADC Architectures II: Successive Approximation ADCs|| The successive approximation ADC has been the mainstay of data acquisition systems for many years. Recent design improvements have extended the sampling frequency of these ADCs into the megahertz region with 18-bit resolution. The Analog Devices PulSAR® family of SAR ADCs uses internal switched capacitor techniques along with auto calibration and offers 18-bits at 2 MSPS (AD7641) on CMOS processes without the need for expensive thin-film laser trimming. At the 16-bit level, the AD7625 (6 MSPS) and AD7626 (10 MSPS) also represent breakthrough technology
|MT-023: ADC Architectures IV: Sigma-Delta ADC Advanced Concepts and Applications|| Tutorial MT-022 discussed the basics of Σ-Δ ADCs. In this tutorial, we will look at some of the more advanced concepts including idle tones, multi-bit Σ-Δ, MASH, bandpass Σ-Δ, as well as some example applications.
|MT-024: ADC Architectures V: Pipelined Subranging ADCs|| The pipelined subranging ADC architecture dominates today's applications where sampling rates of greater than 5 MSPS to 10 MSPS are required. Although the flash (all-parallel) architecture (see Tutorial MT-020) dominated the 8-bit video IC ADC market in the 1980s and early 1990s, the pipelined architecture has largely replaced the flash ADC in modern applications. There are a small number of high power Gallium Arsenide (GaAs) flash converters with sampling rates greater than 1 GHz, but resolution is limited to 6 or 8 bits. However, the flash converter still remains a popular building block for higher resolution pipelined ADCs.
|MT-025: ADC Architectures VI: Folding ADCs|| The "folding" architecture is one of a number of possible serial or bit-per-stage architectures. Various architectures exist for performing A/D conversion using one stage per bit, and the overall concept is shown in Figure 1. A multistage pipelined subranging ADC with one bit per stage and no error correction is basically a bit-per-stage converter. In practice, this type of pipelined converter generally uses a 1.5 bit per stage approach to provide error correction (this is discussed in more detail in Reference 1).
|MT-026: ADC Architectures VII: Counting ADCs|| Although counting-based ADCs are not well suited for high speed applications, they are ideal for high resolution low frequency applications, especially when combined with integrating techniques such as dual-, triple-, and quad-slope.
|MT-027: ADC Architectures VIII: Integrating ADCs|| Soon after the discovery of the basic counting ADC architectures (see Tutorial MT-026) it was realized that much greater accuracy could be obtained using a combination of integrating and counting techniques. This led to the development of high accuracy dual-slope, triple-slope, and quad-slope ADCs. Although the proliferation of high resolution sigma-delta ADCs has made integrating architectures somewhat less popular, they are still used in a variety of precision applications such as digital voltmeters, etc.
|MT-028: Voltage-to-Frequency Converters|| A voltage-to-frequency converter (VFC) is an oscillator whose frequency is linearly proportional to a control voltage. The VFC/counter ADC is monotonic and free of missing codes, integrates noise, and can consume very little power. It is also very useful for telemetry applications, since the VFC, which is small, cheap and low-powered can be mounted on the experimental subject (patient, wild animal, artillery shell, etc.) and communicate with the counter by a telemetry link as shown in Figure 1.
|MT-029: Optical Encoders|| Among the most popular position measuring sensors, optical encoders find use in relatively low reliability and low resolution applications. An incremental optical encoder (left-hand diagram in Figure 1) is a disc divided into sectors that are alternately transparent and opaque. A light source is positioned on one side of the disc, and a light sensor on the other side. As the disc rotates, the output from the detector switches alternately on and off, depending on whether the sector appearing between the light source and the detector is transparent or opaque.
|MT-030: Resolver-to-Digital Converters|| Machine-tool and robotics manufacturers use resolvers and synchros to provide accurate angular and rotational information. These devices excel in demanding factory and aviation applications requiring small size, long-term reliability, absolute position measurement, high accuracy, and low-noise operation.
|MT-031: Grounding Data Converters and Solving the Mystery of "AGND" and "DGND"|| Today's signal processing systems generally require mixed-signal devices such as analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) as well as fast digital signal processors (DSPs). Requirements for processing analog signals having wide dynamic ranges increases the importance of high performance ADCs and DACs. Maintaining wide dynamic range with low noise in hostile digital environments is dependent upon using good high-speed circuit design techniques including proper signal routing, decoupling, and grounding.
|MT-032: Ideal Voltage Feedback (VFB) Op Amp|| The op amp is one of the basic building blocks of linear design. In its classic form it consists of two input terminals, one of which inverts the phase of the signal, the other preserves the phase, and an output terminal. The standard symbol for the op amp is given in Figure 1. This ignores the power supply terminals, which are obviously required for operation.
|MT-033: Voltage Feedback Op Amp Gain and Bandwidth|| This tutorial examines the common ways to specify op amp gain and bandwidth. It should be noted that this discussion applies to voltage feedback (VFB) op amps—current feedback (CFB) op amps are discussed in a later tutorial (MT-034
|MT-034: Current Feedback (CFB) Op Amps|| In this tutorial the two basic op amp topologies—voltage feedback (VFB) and current feedback (CFB)—are discussed in more detail, and the differences are pointed out. The basic voltage feedback op amp along with gain equations is repeated here in Figure 1.
|MT-035: Op Amp Inputs, Outputs, Single-Supply, and Rail-to-Rail Issues|| Single-supply operation has become an increasingly important requirement because of market demands. Automotive, set-top box, camera/camcorder, PC, and laptop computer applications are demanding IC vendors to supply an array of linear devices that operate on a single-supply rail, with the same performance of dual supply parts. Power consumption is now a key parameter for line or battery operated systems, and in some instances, more important than cost.
|MT-036: Op Amp Output Phase-Reversal and Input Over-Voltage Protection|| This tutorial discusses two related topics related to op amps: output phase reversal, and input over-voltage protection.
Output voltage phase-reversal is a problem that occurs in some op amps when the input common-mode (CM) voltage is exceeded. It is usually caused when one of the internal stages of the op amp no longer has sufficient bias voltage across it and subsequently turns off.
|MT-038: Op Amp Input Bias Current|| DEFINITION OF INPUT BIAS CURRENT
Ideally, no current flows into the input terminals of an op amp. In practice, there are always two input bias currents, IB+ and IB- (see Figure 1).
|MT-039: Op Amp Total Output Offset Voltage Calculations|| The equations shown in Figure 1 below are useful in referring all the offset voltage and induced offset voltage from bias current errors to the either the input (RTI) or the output (RTO) of the op amp. The choice of RTI or RTO is a matter of preference.
|MT-040: Op Amp Input Impedance|| Voltage feedback (VFB) op amps normally have both differential and common-mode input impedances specified. Current feedback (CFB) op amps normally specify the impedance to ground at each input. Different models may be used for different voltage feedback op amps, but in the absence of other information, it is usually safe to use the model in Figure 1 below. In this model the bias currents flow into the inputs from infinite impedance current sources.
|MT-041: Op Amp Input and Output Common-Mode and Differential Voltage Range|| Some practical basic points are now considered regarding the allowable input and output voltage ranges of a real op amp. This obviously varies with not only the specific device, but also the supply voltage. While we can always optimize this performance point with device selection, more fundamental considerations come first.
|MT-042: Op Amp Common-Mode Rejection Ratio (CMRR)|| If a signal is applied equally to both inputs of an op amp, so that the differential input voltage is unaffected, the output should not be affected. In practice, changes in common mode voltage will produce changes in output. The op amp common-mode rejection ratio (CMRR) is the ratio of the common-mode gain to differential-mode gain. For example, if a differential input change of Y volts produces a change of 1 V at the output, and a common-mode change of X volts produces a similar change of 1 V, then the CMRR is X/Y.
|MT-043: Op Amp Power Supply Rejection Ratio (PSRR) and Supply Voltages|| If the supply of an op amp changes, its output should not, but it typically does. If a change of X volts in the supply produces an output voltage change of Y volts, then the PSRR on that supply (referred to the output, RTO) is X/Y. The dimensionless ratio is generally called the power supply rejection ratio (PSRR), and Power Supply Rejection (PSR) if it is expressed in dB.
|MT-044: Op Amp Open Loop Gain and Open Loop Gain Nonlinearity|| Open-loop voltage gain, usually called AVOL (sometimes simply AV), for most voltage feedback (VFB) op amps is quite high. Common values are 100,000 to 1,000,000, and 10 or 100 times these figures for high precision parts. Some fast op amps have appreciably lower open-loop gain, but gains of less than a few thousand are unsatisfactory for high accuracy use. Note also that open-loop gain isn't highly stable with temperature, and can vary quite widely from device to device of the same type, so it is important that it be reasonably high.
|MT-045: Op Amp Bandwidth and Bandwidth Flatness|| The open-loop frequency response of a voltage feedback op amp is shown in Figure 1 below. There are two possibilities: Fig. 1A shows the most common, where a high dc gain drops at 6 dB/octave from quite a low frequency down to unity gain. This is a classic single pole response. By contrast, the amplifier in Fig. 1B has two poles in its response—gain drops at 6 dB/octave for a while, and then drops at 12 dB/octave.
|MT-046: Op Amp Settling Time|| The settling time of an amplifier is defined as the time it takes the output to respond to a step change of input and come into, and remain within a defined error band, as measured relative to the 50% point of the input pulse, as shown in Figure 1 below.
|MT-047: Op Amp Noise|| This tutorial discusses the noise generated within op amps, not the external noise which they may pick up due to magnetic and electric coupling. Minimizing this external noise is also important, but in this section we are concerned solely with op amp internal noise.
|MT-048: Op Amp Noise Relationships: 1/f Noise, RMS Noise, and Equivalent Noise Bandwidth|| At high frequencies the noise is white (i.e., its spectral density does not vary with frequency). This is true over most of an op amp's frequency range, but at low frequencies the noise spectral density rises at 3 dB/octave, as shown in Figure 1 above. The power spectral density in this region is inversely proportional to frequency, and therefore the voltage noise spectral density is inversely proportional to the square root of the frequency.
|MT-049: Op Amp Total Output Noise Calculations for Single-Pole System|| We have already pointed out that any noise source which produces less than one third to one fifth of the noise of some greater source can be ignored, with little error. When so doing, both noise voltages must be measured at the same point in the circuit. To analyze the noise performance of an op amp circuit, we must assess the noise contributions of each part of the circuit, and determine which are significant.
|MT-050: Op Amp Total Output Noise Calculations for Second-Order System|| The total output noise for a single-pole system was analyzed in Tutorial MT-049. The circuit shown in Figure 1 below represents a second-order system, where capacitor C1 represents the source capacitance, stray capacitance on the inverting input, the input capacitance of the op amp, or any combination of these. C1 causes a breakpoint in the noise gain, and C2 is the capacitor that must be added to obtain stability.
|MT-051: Current Feedback Op Amp Noise Considerations|| In most applications of high speed op amps, it is the total output rms noise that is generally of interest. Because of the high bandwidths involved, the chief contributor to the output rms noise is therefore the white noise, and the 1/f noise is negligible
|MT-052: Op Amp Noise Figure: Don't Be Mislead|| Op amp noise is generally specified in terms of input current and voltage noise, as previously discussed in MT-047, MT-048, MT-049, MT-050, and MT-051. In communications systems, however, noise is often specified in terms of noise figure (NF)—see Figure 1 below. This can lead to confusion, especially when op amps are used as gain blocks, and the noise figure of the op amp is not specified for the specific circuit conditions.
|MT-053: Op Amp Distortion: HD, THD, THD + N, IMD, SFDR, MTPR|| The dynamic range of an op amp may be defined in several ways. One of the most common ways is to specify harmonic distortion, total harmonic distortion (THD), or total harmonic distortion plus noise (THD + N). Other related specifications include intermodulation distortion (IMD), intercept points (IP2, IP3), spurious free dynamic range (SFDR), and multitone power ratio (MTPR).
|MT-054: Precision Op Amps|| This tutorial examines in more detail some of the issues relating to amplifiers for use in precision signal conditioning applications. Although the OP177 op amp is used as the "gold standard" for precision bipolar amplifiers in these discussions, more recent product introductions such as the rail-to-rail output OP777, OP727, and OP747, along with the OP1177, OP2177, and OP4177 offer nearly as good performance in smaller packages.
|MT-055: Chopper Stabilized (Auto-Zero) Precision Op Amps|| For the lowest offset and drift performance, chopper-stabilized (auto-zero) amplifiers may be the only solution. The best bipolar amplifiers offer offset voltages of 25 μV and 0.1 μV/ºC drift. Offset voltages less than 5 μV with practically no measurable offset drift are obtainable with choppers, albeit with some penalties.
|MT-057: High Speed Current Feedback Op Amps|| We will now examine in more detail the current feedback (CFB) op amp topology which is very popular in high speed op amps. As mentioned previously, the circuit concepts were introduced decades ago, however modern high speed complementary bipolar processes are required to take full advantage of the architecture.
|MT-058: Effects of Feedback Capacitance on VFB and CFB Op Amps|| It is quite common to use a capacitor in the feedback loop of a VFB op amp, to shape the frequency response as in a simple single-pole lowpass filter shown in Figure 1 below. The resulting noise gain is plotted on a Bode plot to analyze stability and phase margin. Stability of the system is determined by the net slope of the noise gain and the open-loop gain where they intersect.
|MT-059: Compensating for the Effects of Input Capacitance on VFB and CFB Op Amps Used in Current-to-Voltage Converters|| Fast op amps are useful as current-to-voltage converters in such applications as high speed photodiode preamplifiers and current-output DAC buffers. A typical application using a VFB op amp as an I/V converter is shown in Figure 1.
|MT-060: Choosing Between Voltage Feedback and Current Feedback Op Amps|| The application advantages of current feedback and voltage feedback differ. In many applications, the differences between CFB and VFB are not readily apparent. Many of today's high speed CFB and VFB amplifiers have comparable performance, but there are certain unique advantages and disadvantages associated with each. This tutorial examines some of the important considerations associated with the two topologies.
|MT-061: Instrumentation Amplifier (In-Amp) Basics|| Probably the most popular among all of the specialty amplifiers is the instrumentation amplifier (hereafter called simply an in-amp). The in-amp is widely used in many industrial and measurement applications where dc precision and gain accuracy must be maintained within a noisy environment, and where large common-mode signals (usually at the ac power line frequency) are present.
|MT-062: Basic Two Op Amp In-Amp Configuration|| In-amps are based on op amps, and there are two basic configurations that are extremely popular. The first is based on two op amps, and the second on three op amps. The circuit shown in Figure 1 is referred to as the two op amp in-amp. Dual precision IC op amps are used in most cases for good matching, such as the OP297 or the OP284. The resistors are usually a thin film laser trimmed array on the same chip.
|MT-063: Basic Three Op Amp In-Amp Configuration|| A second popular in-amp architecture is based on three op amps, and is shown below in Figure 1. This circuit is typically referred to as the three op amp in-amp.
|MT-064: In-Amp DC Error Sources|| The dc and noise specifications for in-amps differ slightly from conventional op amps, so some discussion is required in order to fully understand the error sources.
GAIN-SETTING RESISTOR ERRORS.
The gain of an in-amp is usually set by a single resistor. If the resistor is external to the in-amp, its value is either calculated from a formula or chosen from a table on the data sheet, depending on the desired gain.
|MT-065: In-Amp Noise|| Since in-amps are primarily used to amplify small precision signals, it is important to understand the effects of all the associated noise sources. The in-amp noise model is shown in Figure 1, below.
|MT-066: In-Amp Bridge Circuit Error Budget Analysis|| It is important to understand in-amp error sources in a typical application. Figure 1 below shows a 350 Ω load cell with a fullscale output of 100 mV when excited with a 10 V source. The AD620 is configured for a gain of 100 using the external 499 Ω gain-setting resistor. The table shows how each error source contributes to a total unadjusted error of 2145 ppm. Note however that the gain, offset, and CMR errors can all be removed with a system calibration. The remaining errors—gain nonlinearity and 0.1 Hz to 10 Hz noise—cannot be removed with calibration and ultimately limit the system resolution to 42.8 ppm (approximately 14-bit accuracy).
|MT-067: Auto-Zero In Amps|| Auto-zeroing is a dynamic offset and drift cancellation technique that reduces input referred voltage offset to the μV level, and voltage offset drift to the nV/°C level. The operation of standard auto-zero op amps is discussed in Tutorial MT-055. This tutorial discusses the application of the auto-zero technique to instrumentation amplifiers.
|MT-068: Difference and Current Sense Amplifiers|| A simple subtractor or difference amplifier can be constructed with four resistors and an op amp, as shown in Figure 1 below. It should be noted that this is not an in-amp (see Tutorial MT-061), but it is often used in applications where a simple differential to single-ended conversion is required, such as current sensing.
|MT-069: In-Amp Input Overvoltage Protection|| Instrumentation amplifiers are likely to be subjected to overvoltages when their inputs come from remotely located sensors. If the connecting cable is disconnected and reconnected with the power on, large transient voltages can be generated. Inductive coupling is another mechanism for producing unwanted voltages on the cable that may damage the in-amp input stage.
|MT-070: In-Amp Input RFI Protection|| Real-world applications must deal with an ever increasing amount of radio frequency interference (RFI). Of particular concern are situations in which signal transmission lines are long and signal strength is low. This is the classic application for an in-amp, since its inherent common-mode rejection allows the device to extract weak differential signals riding on strong common-mode noise and interference. One potential problem that is frequently overlooked, however, is that of radio frequency rectification inside the in-amp. When strong RF interference is present, it may become rectified by the internal junctions of the IC and then appear as a dc output offset error.
|MT-071: Analog Isolation Amplifiers|| There are many applications where it is desirable, or even essential, for a sensor to have no direct ("galvanic") electrical connection with the system to which it is supplying data. This might be in order to avoid the possibility of dangerous voltages or currents from one half of the system doing damage in the other, or to break an intractable ground loop. Such a system is said to be "isolated", and the arrangement that passes a signal without galvanic connections is known as an isolation barrier.
|MT-072: Precision Variable Gain Amplifiers|| Most data acquisition systems with wide dynamic range need some method of adjusting the input signal level to the analog-to-digital-converter (ADC). Typical ADC full scale input voltage ranges lie between 1 V and 10 V. To achieve the rated precision of the converter, the maximum input signal should be fairly near its full scale voltage.
|MT-073: High Speed Variable Gain Amplifiers|| High frequency variable gain amplifiers (VGAs) must be fully specified not only in terms of traditional op amp ac specifications (bandwidth, slew rate, settling time), but also in terms of communications-specific specifications. These latter specifications include performance for harmonic distortion, spurious free dynamic range (SFDR), intermodulation distortion, intercept points (IP2, IP3), noise, and noise figure (NF).
|MT-074: Differential Drivers for Precision ADCs|| Many high performance ADCs are now being designed with differential inputs. A fully differential ADC design offers the advantages of good common-mode rejection, reduction in second-order distortion products, and simplified dc trim algorithms. Although they can be driven single-ended, a fully differential driver usually optimizes overall performance.
|MT-075: Differential Drivers for High Speed ADCs Overview|| Many high performance ADCs are now being designed with differential inputs. A fully differential ADC design offers the advantages of good common-mode rejection, reduction in second-order distortion products, and simplified dc trim algorithms. Although they can be driven single-ended, a fully differential driver usually optimizes overall performance.
|MT-076: Differential Driver Analysis|| Differential drivers can be driven by either single-ended or differential signals. This tutorial analyzes both conditions using either an unterminated or a terminated source.
|MT-077: Log Amp Basics|| The term "Logarithmic Amplifier" (generally abbreviated to "log amp") is something of a misnomer, and "Logarithmic Converter" would be a better description. The conversion of a signal to its equivalent logarithmic value involves a nonlinear operation, the consequences of which can be confusing if not fully understood. It is important to realize that many of the familiar concepts of linear circuits are irrelevant to log amps. For example, the incremental gain of an ideal log amp approaches infinity as the input tends to zero, and a change of offset at the output of a log amp is equivalent to a change of amplitude at its input—not a change of input offset.
|MT-078: High Frequency Log Amps|| In Tutorial MT-077 we discussed low frequency log amps. In this tutorial we discuss high frequency applications.
The classic diode/op amp (or transistor/op amp) log amp suffers from limited frequency response, especially at low levels. For high frequency applications, therefore, detecting and true log architectures are used. Although these differ in detail, the general principle behind their design is common to both: instead of one amplifier having a logarithmic characteristic, these designs use a number of similar cascaded linear stages having well-defined large signal behavior.
|MT-079: Analog Multipliers|| An analog multiplier is a device having two input ports and an output port. The signal at the output is the product of the two input signals. If both input and output signals are voltages, the transfer characteristic is the product of the two voltages divided by a scaling factor, K, which has the dimension of voltage as shown in Figure 1.
|MT-080: Mixers and Modulators|| An idealized mixer is shown in Figure 1. An RF (or IF) mixer (not to be confused with video and audio mixers) is an active or passive device that converts a signal from one frequency to another. It can either modulate or demodulate a signal. It has three signal connections, which are called ports in the language of radio engineers. These three ports are the radio frequency (RF) input, the local oscillator (LO) input, and the intermediate frequency (IF) output.
|MT-081: RMS-to-DC Converters|| The root mean square (rms) is a fundamental measurement of the magnitude of an ac signal. Defined practically, the rms value assigned to the ac signal is the amount of dc required to produce an equivalent amount of heat in the same load. Defined mathematically, the rms value of a voltage is defined as the value obtained by squaring the signal, taking the average, and then taking the square root. The averaging time must be sufficiently long to allow filtering at the lowest frequencies of operation desired. We will show a few examples of how efficiently analog circuits can perform this function. More details of rms-to-dc converters can be found in Reference 1.
|MT-082: RF RMS Power Detectors|| The measurement of complex waveforms such as those found in spread spectrum CDMA/W-CDMA and higher order QAM modulation systems has traditionally been a demanding challenge. Analog Devices has developed a range of TruPwr™ detectors that enable the measurement of these complex signals at RF frequencies. The TruPwr™ detectors provide the user with an accurately scaled dc voltage, that is rms equivalent of the input waveform. Within the TruPwr™ range Analog Devices offers products applicable to both wireless and wireline infrastructure applications. and devices packaged in small footprint for portable applications.
|MT-083: Comparators|| A comparator is similar to an op amp. It has two inputs, inverting and non-inverting and an output (see Figure 1). But it is specifically designed to compare the voltages between its two inputs. Therefore it operates in a non-linear fashion. The comparator operates open-loop, providing a two-state logic output voltage. These two states represent the sign of the net difference between the two inputs (including the effects of the comparator input offset voltage). Therefore, the comparator's output will be a logic "1" if the input signal on the non-inverting input exceeds the signal on the inverting input (plus the offset voltage, Vos) and a logic "0" for the opposite case.
|MT-084: Using Op Amps as Comparators|| Even though op amps and comparators may seem interchangeable at first glance there are some important differences. Comparators are designed to work open-loop, they are designed to drive logic from their outputs, and they are designed to work at high speed with minimal instability. Op amps are not designed for use as comparators, they may saturate if over-driven which may cause it to recover comparatively slowly. Many have input stages which behave in unexpected ways when used with large differential voltages, in fact, in many cases, the differential input voltage range of the op amp is limited. And op amp outputs are rarely compatible with logic.
|MT-085: Fundamentals of Direct Digital Synthesis (DDS)|| With the widespread use of digital techniques in instrumentation and communications systems, a digitally-controlled method of generating multiple frequencies from a reference frequency source has evolved called Direct Digital Synthesis (DDS). The basic architecture is shown in Figure 1. In this simplified model, a stable clock drives a programmable-read-only-memory (PROM) which stores one or more integral number of cycles of a sinewave (or other arbitrary waveform, for that matter).
|MT-086: Fundamentals of Phase Locked Loops (PLLs)|| A phase-locked loop is a feedback system combining a voltage controlled oscillator (VCO) and a phase comparator so connected that the oscillator maintains a constant phase angle relative to a reference signal. Phase-locked loops can be used, for example, to generate stable output high frequency signals from a fixed low-frequency signal.
|MT-087: Voltage References|| Voltage references and linear regulators have much in common. In fact, the latter could be functionally described as a reference circuit, but with greater current (or power) output. Accordingly, almost all of the specifications of the two circuit types have great commonality (even though the performance of references is usually tighter with regard to drift, accuracy, etc.). In many cases today the support circuitry is included in the converter package. This is advantageous to the designer since it simplifies the design process and guarantees performance of the system.
|MT-088: Analog Switches and Multiplexers Basics|| Solid-state analog switches and multiplexers have become an essential component in the design of electronic systems which require the ability to control and select a specified transmission path for an analog signal. These devices are used in a wide variety of applications including multi-channel data acquisition systems, process control, instrumentation, video systems, etc.
|MT-089: Video Multiplexers and Crosspoint Switches|| In order to meet stringent specifications of bandwidth flatness, differential gain and phase, and 75 Ω drive capability, high speed complementary bipolar processes are more suitable than CMOS processes for video switches and multiplexers. Traditional CMOS switches and multiplexers suffer from several disadvantages at video frequencies.
|MT-090: Sample and Hold Amplifiers|| The sample-and-hold amplifier, or SHA, is a critical part of most data acquisition systems. It captures an analog signal and holds it during some operation (most commonly analog-digital conversion). The circuitry involved is demanding, and unexpected properties of commonplace components such as capacitors and printed circuit boards may degrade SHA performance.
|MT-091: Digital Potentiometers|| Mechanical potentiometers have been used since the earliest days of electronics and provide a convenient method for the adjustment of the output of various sensors, power supplies, or virtually any device that requires some type of calibration. Timing, frequency, contrast, brightness, gain, and offset adjustments are just a few of the possibilities. However, mechanical pots have always suffered from numerous problems including physical size, mechanical wearout, wiper contamination, resistance drift, sensitivity to vibration, temperature, humidity, the need for screwdriver access, layout inflexibility, etc
|Nanosim|| Synopsys Nanosim is a fast-Spice simulator. It provides near-Spice accuracy at much faster simulation speed. It can be used for full-chip simulation or for functional verification of custom-digital blocks. It also includes dynamic power analysis, a feature previously provided by Synopsys PowerMill.
To the best of my knowledge, Nanosim replaces both PowerMill and TimeMill
|New LabVIEW Function Blocks Based on Industrial Standards|| NI LabVIEW is an intuitive graphical programming language with hundreds of built-in functions for control, analysis, communications, file I/O, and more. The LabVIEW Real-Time Module 8.6 introduces 18 function blocks based on the IEC 61131-3 international standard for programming industrial control systems.
|NI LabVIEW Embedded Evaluation Kit|| The following examples are designed for the National Instruments Embedded Evaluation Platform Kit - including the Single-Board RIO hardware device. The examples demonstrate some of the embedded design capabilities of the LabVIEW FPGA Module and LabVIEW Real-Time Module with the Single-Board RIO evaluation board. For more information regarding the evaluation kit,
|NI-DAQmx Support on Windows XP Embedded|| National Instruments' NI-DAQmx drivers currently support Windows operating systems as well as LabVIEW Real-Time and certain Linux distributions. NI-DAQmx can be used with many common programming languages including ANSI C, C++, C#, and .NET. NI-DAQmx now also supports Windows XP Embedded.
|Norton & Thevenin theorem|| Any voltage network which may be viewed from two terminals can be replaced by a voltage-source equivalent circuit comprising a single voltage source E and a single series resistance R.. The voltage V is the open-circuit voltage between the two terminals and the resistance Z is the resistance of the network viewed from the terminals with all voltage sources removed from circuit
|Ohm's Law|| Ohm's law is the main basic electrical law and defines the resistance of a device to the flow of electrons.
|OpenSPARC Tutorials|| OpenSPARC is the open source version of the UltraSPARC T1 & T2, 64 bit multi-core multi-threaded microprocessors. These tutorials are 12 modules of on-line training by engineers who worked on the creation of the UltraSPARC T1 and T2. OpenSPARC is freely available under GPL 2 at opensparc.net.
|PCI TestBencher Pro|| PCI Example demonstrates how to create PCI master and PCI slave bus-functional models (BFMs) using TestBencher Pro. These are not 100% complete BFMs that can test every feature of the PCI protocol. Instead, they are just partial BFMs to help in the understanding of TestBencher Pro. Each BFM is modeled using a TBP project, which is then instantiated in another project named PCI.hpj. This an excellent example of hierarchical model design how the user can specify ports of slave and master BFMs using the Component Signals & Ports dialog. Some features used in this example include: loop markers, wait until markers, HDL code markers, state variables, simple expect samples, blocking & non-blocking samples, and user defined samples..
|Photodiode Preamp Error Budget Tutorial|| An online tool to illustrate range, gain and accuracy issues in photodiode preamplifiers.
|Pipelining TestBencher Pro|| Pipeline Example demonstrates how pipelined transactors can be created and how they work. To create the pipeline phases, "Pipeline Boundary" Markers were placed on each clock edge that starts and/or ends a pipeline phase. For each "Pipeline Boundary" Marker that starts a phase, a semaphore name is specified. This is done in the "Edit Marker" dialog and can be any valid identifier. To indicate the end of the last pipeline phase, you can either select "End Boundary" as the semaphore name or create an "End Diagram" marker.
|Putting Serial Attached SCSI to Work for You|| Over the past three years, Serial
Attached SCSI (SAS) has been
unveiled as the next evolution of
the SCSI standard featuring
scalability, and reliability, while
maintaining ease-of-use and the
SCSI feature set that has made
SCSI the de facto standard in
environments. The first SAS
products are starting to become
available, and represent the first
step in making SAS a widely
adopted technology standard.
This guide from Adaptec will
help you understand Serial
Attached SCSI: what it is, how it
works, how it can help you get
higher storage performance at a
lower price point, and how to put
this transition to the best use for
your existing storage and future
For many years Adaptec
|Radio Basics|| The term Radio Frequency (RF or rf) refers to the electromagnetic field that is generated when an alternating current is input to an antenna. This field, also called an RF field or radio wave, can be used for wireless broadcasting and communications over a significant portion of the electromagnetic radiation spectrum -- from about 9 kilohertz (kHz) to thousands of gigahertz (GHz). This portion is referred to as the RF Spectrum. As the frequency is increased beyond the RF spectrum, electromagnetic energy takes the form of infrared (IR), visible light, ultraviolet (UV), X rays, and gamma rays."
|Recommended Practices for Using the LabVIEW I/O Variable and NI Scan Engine|| LabVIEW Real-Time 8.6 introduced a new programming model for CompactRIO that reduces development time and complexity. There are several technologies in LabVIEW that make this new programming experience possible, two of which are the NI Scan Engine and I/O variable. To learn more about these features refer to Using NI CompactRIO Scan Mode with NI LabVIEW Software .
|Reduce Embedded Device Costs with NI Single-Board RIO|| Finding the right embedded hardware to deploy quickly is not easy. Traditionally, you would be faced with finding a single-board computer (SBC) with one vendor and then going to another for analog and digital I/O boards. After parts arrive from each vendor, the drivers and integration software effort required to get the entire system communicating stalls actual application development. New NI Single-Board RIO products and LabVIEW embedded software solve this embedded dilemma with eight new NI Single-Board RIO products that combine a real-time processor, a reconfigurable field-programmable gate array (FPGA), and I/O all on one printed circuit board (PCB).
|Reference Design for Automating Simulation using Multisim and LabVIEW|| Through the unique integration between Multisim and LabVIEW, engineers are able to acquire simulation data as easily as real measurements within the LabVIEW environment.
|Regulated Power Supplies|| Observe Baseline operation of regulated power supply below. Then troubleshoot fault one to four below. This voltage regulator simulation uses a battery rather than a rectifier as a power source. Since batteries do not generate ripple voltage, I provided a dynamic load to demonstrate that voltage regulators not only adjust for slow changes in current but can attenuate AC and ripple voltages as well. The frequencies I used were 50, 60, 400, and 1200 hertz corresponding to European, US, Military, and three phase 400 ripple hertz ripple frequencies. Thus, it illustrates effect of regulator on ripple voltage or AC current loads
|Resistors ElectronicsZone Tutorials.|| Begin the tutorials by assuming that you have basic knowledge about electricity like current ,voltage, charges etc.
A resistor is an electronic device that offers obstruction to the flow of electric current
|Resistors in Series & Resistors in Parallel|| A series circuit is one with all the loads in a row. Like links in a chain. There is only one path for the electricity to flow.
|Resource Utilization Statistics for FPGA VIs|| A major consideration when programming FPGAs is the amount of circuitry the code uses on the chip. It is sometimes useful to know how much space a specific funtion, or VI, will use when translated to look up tables (LUTs) and flip-flops. This document includes complete resource utilization statistics for each VI on the FPGA Functions Palette. Due to architectural changes between different FPGA Chip families, each VI will require a different amount of logic on different FPGAs.
|ScopeLink|| Tutorial on ScopeLink
|Selecting the Right FPGA for Your Application|| Field Programmable Gate Arrays (FPGAs) are a tremendously exciting implementation platform. They are used to replace Application Specific ICs (ASICs), such as digital receivers, and programmable general purpose processors or DSPs.
|SEMICONDUCTOR MANUFACTURING|| Semiconductors, sometimes referred to as computer chips or integrated circuits (ICs), contain numerous electrical pathways which connect thousands or even millions of transistors and other electronic components. These transistors store information on the semiconductors, either by holding an electrical charge or by holding little or no charge." from SEMICONDUCTOR MANUFACTURING PROCESS
|Sigma-Delta ADC Tutorial|| An interactive illustration showing the behavior of an idealized sigma-delta A/D converter.
|Signalstorm Library Characterization|| Typically cell libraries contain hundreds of cells and require thousands of Spice runs. This requires extensive CPU power for several days. So the typical goal is to get through the entire flow successfully with 1 or 2 cells, and then to send of the big run.
|SmartTime v7.3 Tutorial|| The SmartTime toolbar contains commands for constraining or analyzing designs. Tool tips are available for each button. This section describes how to enter a clock constraint for the 32-bit shift register pictured in the figure. You will use the SmartTime Constraints Editor and perform post-layout timing analysis using the SmartTime Timing Analyzer.
|Software Product Line Engineering with Feature Models|| Although the term "Software Product line Engineering" is becoming more widely known, there is still uncertainty
among developers about how it would apply in their own development context. In this article we tackle this problem by
describing the design and automated derivation of the product variants of a Software Product Line using an easy to
understand, practical example.
|SPICE Convergence|| Before anything else, build your model using tested models for new devices. Often convergence issues involve these new devices. As an example, consider a behavioral model for a device. Particularly when this model is replicated, especially when it is in a regenerative or a bistable configuration, it can present problems. Why is this?
|Stepping Motors and Robotics|| Stepping motors can be viewed as electric motors without commentators. Typically, all windings in the motor are part of the stator, and the rotor is either a permanent magnet or, in the case of variable reluctance motors, a toothed block of some magnetically soft material. All of the commutation must be handled externally by the motor controller, and typically, the motors and controllers are designed so that the motor may be held in any fixed position as well as being rotated one way or the other.
|Steps to create a back-annotation switching-activity (SAIF) file for DesignPower|| In dc_shell:
|Superposition theorem|| In a network with multiple voltage sources, the current in any branch is the sum of the currents which would flow in that branch due to each voltage source acting alone with all other voltage sources replaced by their internal impedances.
The goal of folowing text is to check superposition theorem.
|Synopsys Pathmill|| This is a quick getting-started guide for Synopsys Pathmill. This tool performs device level static timing analysis and fits into a custom digital flow. For a standard-cell based flow there are better tools available, most notably Synopsys Primetime and Cadence First Encounter timing analysis. Pathmill is most often used for timing analysis of circuits in domino logic or other high speed custom digital logic.
|Synplify Pro to improve performance in Altera FPGAs|| This tutorial describes preferred ways to set up your design and four methods of fine-tuning synthesis to improve performance or reduce the area in Altera FPGAs.
|SystemVerilog DPI Tutorial|| Direct Programming Interface or DPI is an interface between SystemVerilog and C that allows inter-language function calls. This means a SystemVerilog task or function can call a C function. And conversely, a C language function can call a SystemVerilog task or function. A C function call from the SystemVerilog side will look identical to any other SystemVerilog task or function call. Similarly, a SystemVerilog task or function call from the C side is no different from any other C function call (see Figure 1). And best of all, you can do all these without any knowledge or overhead of PLI or VPI.
|Taking the Mystery out of the Infamous Formula, "SNR=6.02N + 1.76dB," and Why You Should Care|| You don't have to deal with ADCs or DACs for long before running across this often quoted formula for the theoretical signal-to-noise ratio (SNR) of a converter. Rather than blindly accepting it on face value, a fundamental knowledge of its origin is important, because the formula encompasses some subtleties which if not understood can lead to significant misinterpretation of both data sheet specifications and converter performance.
|Text processing with awk|| awk is an utility to process text files. Text files are in IC design: SPICE netlists, LEF files, DEF files, Verilog, SPEF, and so on.
|The Network’s Architecture|| The relationship between connected devices in a network determines the network’s overall
architecture. The most common architecture types for networks are peer-to-peer, client/
server, and hybrid architectures.
Peer-to-peer architectures are network implementations in which there is no centralized area
of control. Every device on the network must manage its own resources and requirements.
Devices all communicate as equals, and can utilize each other’s resources. Peer-to-peer
networks are usually implemented as LANs because, while simpler to implement, this architecture
creates security and performance issues related to the visibility and accessibility of
each device’s resources to the rest of the network.
Client/server architectures are network implementations in which there is a centralized
device, called the server, in control that manages most of the network’s requirements and
resources. The other devices on the network, called clients, contain fewer resources and
must utilize the server’s resources. The client/server architecture is more complex than the
peer-to-peer architecture and has the single critical point of failure (the server). However,
it is more secure than the peer-to-peer model, since only the server has visibility into other
devices. Client/server architectures are also usually more reliable, since only the server has
to be responsible for providing redundancy for the network’s resources in case of failures.
Client/server architectures also have better performance, since the server device in this type of
network usually needs to be more powerful in order to provide the network’s resources. This
architecture is implemented in either LANs orWANs.
Hybrid architectures are a combination of the peer-to-peer and client/server architecture models.
This architecture is also implemented in both LANs andWANs.
|The Role of B2 Spice A/D v4|| Designing a power supply with 4 DC outputs:
Many reference designs can be found on the Internet. However, estimating total current draw or available voltage when configuring the regulators can be done very quickly using the operating point simulation in B2 Spice.
|The stepper motor assistant|| B2 Spice can be used to display the operating point of a stepper driver circuit. It can also be used to perform parameter sweeps in order to see the correct voltage or current limiting resistor values for L-R drive circuits.
|The TCL Scripting Language|| Most software tools require a scripting/batch/macro language. In the past this meant that the user had to learn a new language for each software package. This is clearly inefficient, both for the user but also for the company. They shouldn't really spend their time creating languages.
This is where TCL comes into play. It is a scripting language that can readily be used in any application. As a result, essentially all modern EDA tools now use TCL (e.g. Cadence Encounter, RTL Compiler and Synopsys Design Compiler). It just makes sense.
|Transistors and Diodes|| Diodes and Transistor Circuits
|Tutorial for Using Identify® with Libero® Integrated Design Environment (IDE)|| Identify is an RTL Debugger that allows you to probe internal signals of the design and view those
signals directly from the programmed FPGA in the original RTL code or in a waveform viewer.
Identify consists of two separate tools: Instrumentor and Debugger. The instrumentor compiles and
inserts the necessary logic into the original RTL to create an instrumented design that allows
probing of internal signals. The Debugger communicates to the FlashPro, FlashPro Lite, or
FlashPro3 device via JTAG to get the values for the probed signals directly from the programmed
FPGA, and displays those signals.
This tutorial shows how Identify Instrumentor and Debugger can be used within the Libero IDE
flow. It also explains how Identify Instrumentor works with Synplify AE. It gives you step-by-step
instructions with image snapshots of the tools.
|Tutorial On Generating Variants Using XSLT|| This tutorial demonstrates how to generate a variant using XSLT transformations on the
example of a simple shop project. The products sold in the shop, i.e. laptops, consist of the
same components in different variants. According to the chosen product, an order form
shall be generated listing the components, the price of each component, and the total sum
of the order. This order form shall be plain HTML that is generated using an XSLT script
executed in an XSLT transformation.
|Tutorial on text transformation with pure::variants|| This tutorial shows how to perform text transformations using the source elements
ps:fragment, ps:condtext, and ps:condxml.
|Tutorials on VHDL|| In hardware development VHDL and Verilog are the prominent languages in the design flow of a digital system. This tutorial focuses on VHDL. Although hardware engineers use VHDL, many of them are not aware of the features of VHDL that can be very useful to them. Most engineers use VHDL at the register transfer level (often only a synthesisable subset of VHDL). This frequently led to unnecessary complex, and unreadable, descriptions. After some time it is recommended that VHDL users brush up their VHDL knowledge to improve their use of VHDL.
|UARTTEST TestBencher Pro|| UART Example demonstrates how to design a Universal Asynchronous Receiver/Transmitter (UART) controller which is the key component in serial bus communications. The UART takes bytes of data and transmits the individual bits in a sequential fashion. At the destination, a second UART re-assembles the bits into complete bytes. This project contains three transactors: CLK_generator, WriteSerial, and ReadSerial. In this example, the WriteSerial and ReadSerial transactors communicate with each other. They send and receive serial data on a signal named UART. But, they work with parallel data at the transactor level. For example, the write transactor has an eight bit argument which it then converts to serial data. Both of these diagrams also have a parameter named "speed" which controls how many clock cycles are to be used for each bit of data.
|Ultra High resolution Encoding (More than 8K)|| The PRISTINE radically accelerates JPEG 2000 encoding and decoding while supporting a wide range of resolutions up to 4K+ (4096x3112). Combining several PRISTINEs give access to higher resolutions, like the Ultra High Resolution 8K. Embedded intoPIX technology allows both Mathematically and Visually Lossless compression providing the ultimate in pristine picture quality.
|Unix tricks|| When people first see a Unix command line they might think "Oh boy, lots of typing. I wish I was in Windows, where I can click on everything".
But the Unix command line comes stocked with lots of useful tools. The more of them you know the faster you can work. Pretty soon you can use the command line to do tasks in seconds that would require dozends of mouse clicks in Windows.
|Using C-Language Simulation for Algorithm Verification|| This Getting Started tutorial describes the process of C-language simulation, by showing how you can compile your C-language hardware module along with test producer and consumer processes to verify correct behavior. This tutorial builds on what you learned in the first tutorial (Creating VHDL and Verilog from C-Language). This tutorial concludes with additional discussions of multiple-process parallelism, hardware generation and pipeline optimization.
|Using Circuit Magic to find Norton & Thevenin equvalents|| Sample circuit
|Using DirectCore in Libero IDE v8.4|| Actel produces Intellectual Property (IP) functional cores, called DirectCores, which are designed and optimized for use with Actel devices. The Actel Libero IDE tool offers simple implementation of these DirectCores into a design. The goal of this document is to explain how to generate DirectCores in Libero IDE v8.4, and instantiate them into a design. The terms "DirectCore" and "Cores" are used
interchangeably in this document.
|Using NI CompactRIO Scan Mode with NI LabVIEW Software|| The LabVIEW Real-Time Module 8.6 introduces powerful new features for programming CompactRIO hardware that reduce development time and complexity as well as provide tools for monitoring and maintaining CompactRIO applications. CompactRIO is a high-performance programmable automation controller (PAC) that is differentiated by a field-programmable gate array (FPGA) at the heart of its architecture.
|Using the Cycle-Accurate ARM Microcontroller Simulator|| The LabVIEW Embedded Module for ARM Microcontrollers includes support for the RealView µVision ARM simulator, which provides cycle accurate timing and logic simulation. In addition, the simulator supports many of the on-chip peripherals so that you can provide controlled stimulus and response for debugging and testing your application.
|Variable Capacitor|| It would seem trivial to create a voltage-variable capacitor. One could just pass parameter variables to a capacitor's capacitance. Simple
or is it?
|Variable Inductor|| would seem trivial to create a voltage-variable inductor. One could just pass parameter variables to an inductor's inductance. However, just as in the case of the variable capacitor, one must first look to the defining equations for an inductor.
|Variable Transformer – A Building Block|| Harvey Morehouse is a contractor/consultant with many years of experience using circuit analysis programs. His primary activities are in Reliability, Safety, Testability and Circuit Analysis. He may be reached at firstname.lastname@example.org. Simple questions for which I know the answer are free. Complex questions, especially where I am ignorant of the answers, are costly!!!
|Verilogger Pro Animated Tutorial|| Verilogger Pro from SynaptiCAD: Animated Tutorial Version 7.0
|Verilogger Pro: Basic Tutorial|| This tutorial demonstrates how to use the project window to complie and stimulate Verilog source code. It also demonstrates the unit level testing features that let you graphically draw a test bench and link it to the model under test.
|Video Tutorial: How to Achieve Early Formal Convergence with Oski Abstraction Models|| Decoding Formal Video Tutorial Series: How to Achieve Early Formal Convergence with Abstraction Models
The state space for formal is huge, and formal tools are limited by design size and where the proofs stop converging. This video tutorial discusses how abstraction models can be used to transform the search space for a formal verification run, and bring states which are distant close to the search state, allowing the proofs to converge much faster.
|Video Tutorial: How to Know When a Formal Testbench is Complete|| Decoding Formal Video Tutorial Series: How do you know when your formal testbench is complete? This is an important problem, because if you have decided to replace simulation with formal verification on a block you are working on, you want to know when to sign off with the work you have done. This tutorial discusses three factors that determine whether or not you are done with your formal testbench: constraints, checkers, complexity.
|Video: How to Formally Verify - and Reuse - Highly Configurable IP Designs|| Decoding Formal Video Tutorial Series: How to Formally Verify and Reuse Highly Configurable IP. Many designs today support all kinds of IPs which need to be verified. Tight schedules mean the only choice may be 3rd party IP or to re-use internal IP. The designs are very configurable and the IPs themselves are highly configurable, and the problem is that there are billions of different configurations. The beauty of formal verification is that you can try all of these different configurations together by making them a symbolic constant. Verifying IP, especially highly configurable IP becomes extremely valuable if you do it with formal because you get a level of coverage that is almost impossible to get with simulation.
|VME TestBencher Pro|| VME Example demonstrates how you would create bus-functional models (BFMs) for the arbiter, master, and slave VME components. It also shows one way to configure a set of slave BFM instances to respond to different address ranges. Each of these BFMs are represented by a TestBencher Pro project which are all instantiated in a top-level project named VME.hpj. This entire example is composed of unclocked diagrams.
|VNC Remote Access Tutorial|| This tutorial describes how VNC makes it easy to remote controll any machine on the internet and to share one desktop with many users.
Consider some of the benefits of VNC over X11
|Voltage, Current & Resistance|| In electronics we are dealing with voltage, current and resistance in circuits.
|WaveFormer Pro: Basic Tutorial|| WaveFormer Pro Animated Tutorial
1.0 Draw a Waveform
|What Is an Embedded System?|| An embedded system is an applied computer system, as distinguished from other types of computer
systems such as personal computers (PCs) or supercomputers. However, you will find
that the definition of “embedded system” is fluid and difficult to pin down, as it constantly
evolves with advances in technology and dramatic decreases in the cost of implementing various
hardware and software components. In recent years, the field has outgrown many of its
traditional descriptions. Because the reader will likely encounter some of these descriptions
and definitions, it is important to understand the reasoning behind them and why they may
or may not be accurate today, and to be able to discuss them knowledgeably
|X-ray detector arrays for dental, medical and security applications (Tutorial "X-Ray Detectors")|| The photographic film is the most widely used detection medium in X-ray imaging applications. It has been used since the discovery of X-rays at the end of the last century. But the principal disadvantage of the X-ray film is its low sensitivity due to the poor absorption. Only about 1 % of the incoming radiation is absorbed in the film. In addition the film needs to be chemical developed before it can be viewed. Major advantage of course is the fact that the film area can be large.