Verific Design Automation: Standing tall

If you’re in EDA and haven’t heard of Verific Design Automation, it would appear you haven’t been listening. Michiel Ligthart, Verific President and COO, told me in a recent phone call that few people in the industry are unaware of his company’s offerings: “We’re very well known in the industry. Everybody who works in EDA knows us, or if they don’t, we are no more than 2 or 3 phone calls away.

“Verific is a little bit different kind of company. We are a small solutions providers, but we do not have an end-user product. Instead, we provide SystemVerilog and VHDL parsers that we license to EDA companies, and to semiconductor companies that build EDA products for internal use or for their customers.”

I asked why such companies don’t build their own parsers, and he said, “In fact, they could. These are based on IEEE standards and anyone could build them, but the parsers must be the same for everyone. If you can buy them from somebody else, rather than build them, it means you can concentrate on your distinctive solutions. Verilog parsers from companies like Cadence or Synopsys all have to adhere to the same standard.”

Could Verific become an EDA company?

Michiel Ligthart responded: “If we created an end-user solution, we would be competing with some of our licensees. Currently, we have more than 60 licensees, with parsers in customers’ products [ranging] from synthesis, to formal verification, to debug, test solutions, and linting. You name it, someone has used our standard SystemVerilog or VHDL parser in their EDA solution.”

When and how did the company begin?

Ligthart said, “Verific was founded in 1999 by Rob Dekker. Rob and I both came out of Exemplar, a logic synthesis company for FPGAs that was acquired by Mentor Graphics in 1996.

“Rob and I stuck around Mentor until 1999 and then he left to found Verific, although at that point he didn’t know what it was become, and I left Mentor to join an asynchronous semiconductor company. It turned out to be a great company, building asynchronous semiconductors and the tools, but in the end it was a solution to a non-existent problem.

“In the meantime, Rob had written his parsers and started Verific because he was going to do verification. So many people were interested in his parsers, however, [he moved in that direction] instead. Then in 2003, Rob asked me to team up with him at Verific. This coming Labor Day, I will be celebrating 10 years with the company.”

I asked where Verific is located, and Ligthart said, “The company has offices in Alameda, next to Oakland, and we also have operations in Calcutta because we believe in outsourcing. At Exemplar, we were working with an engineer, Abhijit Chakrabarty, who decided to return to India after several years. We asked him to work with us from Calcutta, and that has worked out really well.

“We were also able to hire a few more re-repatriated Indian engineers, many with degrees from IIT, who had previously worked in California. We have some fine engineering talent in Calcutta and have  been very fortunate, because of their background at ITT and because their experience in California makes them aware of how American high-tech companies function.”

Where are Verific’s customers located?

Ligthart said, “They are worldwide. Even though the EDA startups tend to be in the Silicon Valley area, as well as the semiconductor companies, we see a fair amount of development in India and China. So even though our licensees may have San Jose-based headquarters, the work may be done in India or China. We also have customers in Europe and Israel.”

Does that translate into a lot of travel time for the Verific team?

Ligthart said, “Our customers don’t actually need field support. We can handle it all between email and web casts. It’s not necessary to fly in and interrupt people, which says something about the quality of our software.

“Traditionally, there are large field services in EDA companies. The moment something goes wrong, someone flies in and looks at the problem. With our software, however, that’s not necessary. If there’s a problem, most people can figure it out with a simple defect report.

“Everything else is done by web conference. If you have a product that is easy to explain and does not require enormous amounts of maintenance and hand-holding, that’s easy to do. Which is what we have hammered on from day one: The quality of the software, and that it should be maintenance free.”

So how does Verific find new customers?

Ligthart reiterated: “Normally at this point, our customers find us. Nonetheless, we always go to DAC and DVCon, where we speak with new prospects. There are always people who may not have immediate need for us, but when they do, they will know how to reach us. In the EDA world, anybody who has to tackle SystemVerilog knows to call us. We may be less well known among the semiconductor companies, but we have seen a lot of internal projects.

“Basically, when people have a problem they need to solve, they look around and see we have an existing solution. Perhaps they think about building a quick-and-dirty parser, but more often they call us for something far better. What we have seen is that this kind of potential user doesn’t necessarily like to program in C++, preferring tcl or Perl – they’re semiconductor engineers, not programmers.”

I asked how much the Verific products have evolved over the 10 years Ligthart has been with the company.

He said, “Heavily! It was originally developed for Verilog-1993, but when SystemVerilog came out, we had to do major rethinking and research into the product. We set up the right architecture from the start, however, so everything then became incremental. We do monthly releases, and with every release we fix defects.

“We also do development for supporting new standards. SystemVerilog-2009, for instance, has been a big, big effort for us. Even though SystemVerilog-2012 has just come out, we are not yet done with SystemVerilog-2009, which is not uncommon in the industry.

“Synopsys VCS, Mentor Questa, and Cadence Incisive – they have not yet been updated. It’s very difficult and a lot of work, with things continuously changing. It’s the same for VHDL-2008, which came out 5 years ago. Now in the last 2 years, we’ve seen more and more interest in that standard.

“Meanwhile at DAC 2011, we introduced a Perl API to our SystemVerilog and VHDL parsers that has gotten a lot of traction in the last year and a half. We have also seen a lot of semiconductor companies using our tools heavily.”

Speaking of DAC, what’s with the legendary Verific giraffe giveaways?

Ligthart laughed: “When we stared working on our marketing, we wanted a mascot for the company. We looked around and saw that the giraffe is both nice and goofy. It’s everybody’s friend, is not predatory, doesn’t have any real enemies, and will stick its neck out for you. We decided to give it a try and clearly people loved it.

“Now we have it on our website, and in our booths at DAC and DVCon we have the stuffed giraffes. It’s true several people at Verific are very tall, but that realization only came afterwards. It was the image of the giraffe and what it represented that we thought of first.”

He laughed again, “We like to say that Verific stands heads and shoulders above the competition!”

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Tags: Abhijit Chakrabarty, Michiel Ligthart, parsers, Rob Dekker, SystemVerilog, Verific Design Automation, VHDL

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