Automatically Generating Interacting, Self-Checking Test Cases for 144 CPU Cores

We hope that the title of this blog post piqued your interest, because we don’t believe that we’ve seen anyone anywhere claiming to do automated multi-SoC verification at this level. Two weeks ago, we previewed next week’s Design and Verification Conference and Exhibition (DVCon) in San Jose. We highlighted one particular talk being co-presented by Breker and Cavium on “Using Portable Stimulus to Verify Cache Coherency in a Many-Core SoC” in the 9:00-10:30 a.m. session on Tuesday, March 1.

We teased you with the statement that this talk will describe “generating test cases for a multi-SoC configuration with well over 100 cores” and it’s time to tell you a bit more now that we have issued a press release on our project with Cavium. Of course, we need to reserve some of the details for the paper in the DVCon proceedings and the talk itself so that new material is being presented at the conference. We heartily encourage you at attend the show and hear for yourself.

Cavium designs and verifies some of the biggest chips in the world, including  data center and cloud processors with 48 CPU cores. Some time back, they selected our Trek family of products to help them verify this large number of processors in parallel. They were especially worried about cache coherency, since the 48 cores have caches and are connected by a coherent fabric. The entire SoC has to be cache-coherent across all the cores, which requires specialized test cases that comprehend cache line sizes and cache state transitions.

But verification didn’t stop there. The latest architecture from Cavium includes a coherent processor interconnect that can link two 48-cores SoCs together in a dual-socket configuration. As the interconnect name implies, coherency is maintained across the link and so all 96 CPU cores must be verified to be completely cache-coherent. Our Trek products were used to verify this configuration as well, a demonstration of our multi-SoC capabilities that we discussed in a recent post.

But verification still didn’t stop there. The Cavium team wanted to verify a third SoC linked to the dual-socket pair by a PCI Express (PCIe) Gen3 connection. So we also generated test cases to verify all three SoCs together, containing a total of 144 CPU cores, 96 running cache coherency tests and 48 generating PCIe traffic. To be clear, the 144 programs we generated were not independent; all test cases were self-checking and multi-threaded, with the CPUs interacting and interleaving.

We automatically generated the 144 programs from our graph-based scenario models, including the pre-built model supplied with our Cache Coherency TrekApp. Cavium used TrekSoC-Si to stitch the test cases together, downloaded the programs into actual chips in the bring-up lab, and ran them. Our TrekBox run-time module executed on the lab’s host machine to monitor test case progress, extract coverage metrics, and provide debug information whenever a test case failed.

But verification still didn’t stop there.  Although the primary focus of this particular project was verifying the multi-SoC project in silicon, Cavium has also run some of the smaller test cases in simulation. This demonstrates that the Breker approach achieves the goals of portable verification testing as defined by the Accellera Portable Stimulus Working Group (PSWG). Summarizing: Cavium benefited from automatically generated portable, self-checking, interacting, many-core, multi-SoC test cases.

Please join us for this amazing talk at DVCon on Tuesday morning. Please also remember that our CEO Adnan Hamid will be on the “Redefining ESL” panel on Wednesday, March 2, 8:30 – 9:30 a.m. Finally, Breker will be exhibiting on Monday, February 29, 5 – 7 p.m., and Tuesday and Wednesday, March 1-2, 2:30 – 6 p.m. All events will be held in the Doubletree Hotel in San Jose. See you there!

Tom A.

The truth is out there … sometimes it’s in a blog.

Tags: application, Breker, bring-up lab, cache coherency, Cavium, dvcon, emulation, FPGA, functional verification, graph, graph-based, multi-SoC, node coverage, path coverage, portable stimulus, prototyping, PSWG, realistic use case, scenario model, simulation, SoC validation, SoC verification, system-on-chip, test case generator, test cases, TrekSoC-Si, Universal Verification Methodology, use-case coverage, uvm

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