The Evolution of DesignCon and Why Breker Isn’t There

One of the most popular posts in the history of The Breker Trekker was one discussing which conferences were most useful for verification engineers. I mentioned that Breker exhibited at the annual Design and Verification Conference (DVCon) in San Jose, and we’ve since published several popular posts about that show. It remains the most important event for us, our customers, and the functional verification industry in general. We will be there again in March, and will provide more information in an upcoming post.

I also mentioned the DesignCon show, held annually in Santa Clara, but did not list it among those that we attend. I always go and walk the floor for an hour or two to say hello to old friends and to see what’s new. However, Breker does not exhibit at this show and is highly unlikely to do so unless there are significant changes in its focus and attendance. This is not a criticism of the show, just an observation. Since DesignCon is happening this week, I thought that it might be fun to review its history and how it has changed.

I’ll start with the confession that I have a soft spot for this show. I first attended it way back in 1997, when it was known as Design SuperCon. From that point, I had a nearly unbroken streak for 12 years. I presented a paper, participated in a panel, or both, every year from 1997 through 2008 except 2003. I also presented papers at two DesignCon East events, appearing in a total of more than a dozen sessions. Also in 2008, Breker CEO and co-founder Adnan Hamid appeared on a panel, presented a talk, and won a DesignCon Paper Award.

I mention this history to show how welcoming DesignCon was to front-end digital design and verification. Adnan of course talked about Breker’s graph-based verification. My talks and panels covered such topics as designing with  synthesizable cores, reusability standards, coverage metrics, SystemVerilog assertions, and formal analysis. DesignCon even recruited verification guru Brian Bailey to build high-quality tracks for front-end topics such as functional verification and electronic system-level (ESL) design. For example, the 2006 program included:

• Case studies on designing a DDR2 memory controller, an HDTV encoder, and PCI Express IP
• Case studies on verifying a multi-Gb transceiver IP and a multithreaded microprocessor
• Three case studies on assertion usage and two proposals for better verification planning
• An ESL taxonomy and a tutorial on SystemC transaction-level model (TLM) usage

Now that’s a list of papers that would make even DVCon proud. Compare that with this week’s DesignCon program. I counted about 130 talks and tutorials, and saw only two or three that sounded as if they might relate to digital design, with nothing at all about functional verification. The focus is almost entirely on analog design and analysis. 12 talks have “jitter” in their titles, 11 have “integrity” (signal or power), and 9 have “electromagnetic” (or “EMI”). Yes, DesignCon has changed a lot since the days when I was a frequent and active participant.

I realized the change when I had a couple of proposals rejected in the 2009-2012 timeframe. Knowing that power is a big topic in the “new” DesignCon, in 2013 I managed to craft a proposal for “Cracking the Challenge of SoC Low-Power Verification” that was accepted. Both EDN and Electronic Engineering Times called out my talk as one of the must-sees for the upcoming show, but I was disappointed by a small turnout. From their body language and the questions afterward, it was clear that this was entirely the wrong audience to hear about Breker’s graph-based scenario models.

So that is why we do not exhibit or speak at DesignCon. The industry cliché is that DesignCon has become a show only for designers and that DVCon has become a show only for verification engineers. I think that’s a facile and misleading statement. DesignCon is the show for analog and transistor-level design and analysis. DVCon is the show for digital and system-level design and verification. Both conferences do a fine job in their respective domains. I may happen to catch you on the floor at DesignCon, but I will surely see you in the Breker booth at DVCon.

Tom A.

The truth is out there … sometimes it’s in a blog.

Tags: Breker, Design SuperCon, DesignCon, dvcon, EDA, functional verification, integration verification, IP, standards, TrekUVM, verification IP, VIP

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