The Breker Trekker
Tom Anderson, VP of Marketing
Tom Anderson is vice president of Marketing for Breker Verification Systems. He previously served as Product Management Group Director for Advanced Verification Solutions at Cadence, Technical Marketing Director in the Verification Group at Synopsys and Vice President of Applications Engineering at … More »
Report from the Silicon Valley IP Users Conference
October 16th, 2014 by Tom Anderson, VP of Marketing
I spent Tuesday of this week in the Winchester Mystery House, San Jose’s best-known tourist attraction, hearing a wide variety of opinions about design IP, verification IP (VIP), the Internet of Things (IoT), and related topics. “Unlock the Mystery of IP: Silicon Valley IP Users Conference” was organized and presented by IPextreme and their Constellations program partners. I found most of the talks quite interesting, and would like to share some thoughts on what the experts’ projections might mean for Breker and our customers.
There is no doubt that the increasing use of IP is key to designing ever larger chips. Kands Manickam of IPextreme noted that, over the next five years, the compound annual growth rate (CAGR) of IP blocks and subsystems is expected to be 12% versus 3.5% for semiconductors. Randy Smith of Sonics reported that the average large chip today has about 120 blocks, growing to more than 200 by 2018. We already know that VIP reuse is not as effective as design IP reuse, and these projections will only exacerbate the gap.
Although it didn’t come up explicitly in the discussions, some industry observers argue that increased use of design IP has actually made verification harder. If the IP vendors do not deliver reusable VIP then the development team is faced with trying to verify a chip containing significant portions that they didn’t design and don’t understand. As we’ve discussed in this blog before, traditional forms of VIP are not very reusable. If the IP providers shipped graph-based scenario models they would make chip verification a far easier task.
There was also some interesting discussion on the merits of reusing in-house designs versus acquiring commercial IP. The panel “IP Subsystems: Build or Buy?” assessed the risks of acquiring IP internally, concluding that users are less likely to change (and possibly break) externally-acquired IP. Also, support and documentation are more likely to be provided by commercial IP vendors. Warren Savage of IPextreme lists “no documentation” as one of the top 10 reasons why (internal) IP reuse fails.
Verification was mentioned a few times; I think that the lack of VIP is also a key reason why reuse doesn’t always work as well as expected within the same company. There is a simple solution: the IP block developers should create scenario models and use TrekUVM or TrekSoC as a key part of their verification. The models they produce can be reused directly by subsystem and chip-level verification teams, solving the long-standing problem of verification reuse lagging behind design reuse.
I was especially interested in the sessions devoted to the IoT. Jim Feldhan of Semico Research Corporation said that they project 35 billion connected devices by 2020. Every one of those devices will have at least one complex chip, almost certainly an SoC, so that software can be used to customize common hardware. The key “mystery” is the question that I asked the IoT panel at this conference. Will there be hundreds of such devices developed or only a few programmable platforms that will be able to span the majority of IoT applications?
I really liked the answer I heard from Tom Quan of TSMC: for the foreseeable future, there will be many different SoCs developed for IoT. This is partly due to the wide range of sensors needed for different domains; building a “super IoT chip” with many different sensors would mean that each user pays for unneeded silicon that might not be offset by the higher volumes manufactured. There were a few references to Makimoto’s Wave, which shows how the chip industry oscillates between customization and standardization. We’re now in a period of SoC customization.
I concluded that the IoT offers a great opportunity for Breker. Many of you will be spinning application-centric SoCs with few design changes for each variation, on very tight schedules that will permit no chip turns. This will put more pressure than ever on verification. Our ability to reuse scenario models from block to chip, across verification platforms, and between projects will be essential to meet IoT schedule and quality goals.
Thanks to IPextreme for their stimulating event, including a free tour of the Winchester Mystery House, and for spurring my thinking about what the IoT will mean to us all.
The truth is out there … sometimes it’s in a blog.
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