Ladies and Gentlemen, Step Right Up!

As I mentioned in my debut post, this blog will be a mix of technical information, industry commentaries, and updates on Breker and our team. This time I’d like to fill you in on some of the activities that have kept us busy so far in 2013. In the EDA industry, most of the major conferences and tradeshows occur in the first half of the year, while most of the sales happen in the second. That’s not coincidental. New products are introduced at the events, users generally evaluate them in mid-year, and Purchasing departments usually want to close deals before the end of the calendar year.

Accordingly, we at Breker have been very busy with a series of shows in 2013. The biggest event so far was the Design & Verification Conference and Exhibition, better known as DVCon. Held in the San Jose DoubleTree hotel, the focus has shifted over the years to verification, with very little emphasis on design. Perhaps that’s due to another local show called DesignCon about a month earlier. Breker was at DVCon in force, with a spiffy new booth graphic to explain our SoC verification flow.

We also sponsored a breakfast panel that posed the question “How Does Anyone Tape Out Working Chips Anymore?” Moderated by EDA journalist Brian Bailey, the panelists debated the merits of Breker’s TrekSoC solution and other technologies for full-chip verification. We managed to arrange a nice spectrum of panelists (left to right):

• Poonam Singh from Broadcom, an active TrekSoC user
• Adnan Hamid, Breker CEO and inventor of the TrekSoC technology
• Mark Glasser from Cypress, not a TrekSoC user
• Jon Michelson from NVIDIA, not a  TrekSoC user although NVIDIA is a customer

Breker has been exhibiting at DVCon and the Design Automation Conference (DAC) for several years, but in the last few months we’ve been expanding our participation in conferences and tradeshows as TrekSoC moves into the verification mainstream. For example, our Indian distributor CMR exhibited at Verification Futures India and presented a talk on TrekSoC. Also in March, we attended CDNLive Silicon Valley, the Cadence users group event, for the first time. It was lively and informative, with good interest from the attendees.

A couple weeks later found us at SNUG Silicon Valley, the main annual event for Synopsys users. My sense was that SNUG had a higher concentration of verification engineers than did CDNLive, and again we had a lot of fun chatting with users. I assisted at numerous CDNLive and SNUG events while working at Cadence and Synopsys, but it was quite different attending as a partner. I hoped to make it “3 for 3” but the Mentor user group meeting this year did not have an exhibition for other vendors.

In the second half of the year we will likely exhibit again at ARM TechCon in Silicon Valley and the SoC Conference in Irvine. Right now we’re eagerly anticipating DAC, in fact the 50^th year for that show, being held in Austin for the first time. Please tune in to our May blog posts, when we’ll talk a lot about what’s happening at DAC. Above all, if you find yourself at any EDA show please check for our name in the exhibitor list and conference program. We would love to have you stop by and say hello.

Tom A.

The truth is out there … sometimes it’s in a blog.

Tags: arrm techcon, Breker functional verification SoC verification Trek TrekSoC, dac, dvcon, socc, verfication futures

This entry was posted on Tuesday, April 23rd, 2013 at 5:52 pm. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.